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Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/1097-024x(200009)30:11<1203::aid-spe338>3.0.co;2-nopenalex-snapshot
An open graph visualization system and its applications to software engineering
inferredcites →https://doi.org/10.1109/54.867894openalex-snapshot
RT-level ITC'99 benchmarks and first ATPG results
inferredcites →https://doi.org/10.1109/cloudcom.2015.60openalex-snapshot
Virtualized FPGA Accelerators for Efficient Cloud Computing
inferredcites →https://doi.org/10.1109/ets.2012.6233026openalex-snapshot
Multi-conditional SAT-ATPG for power-droop testing
inferredcites →https://doi.org/10.1109/fccm.2018.00016openalex-snapshot
FPGA Side Channel Attacks without Physical Access
inferredcites →https://doi.org/10.1109/fpl.2010.117openalex-snapshot
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
inferredcites →https://doi.org/10.1109/fpl.2012.6339242openalex-snapshot
FPGAs for trusted cloud computing
inferredcites →https://doi.org/10.1109/iscas.2003.1206140openalex-snapshot
Proceedings Of The 2003 IEEE International Symposium On Circuits And systems
inferredcites →https://doi.org/10.1109/lpe.1996openalex-snapshot
Proceedings of 1996 International Symposium on Low Power Electronics and Design
inferredcites →https://doi.org/10.1109/mdt.2007.79openalex-snapshot
Power Supply Noise in SoCs: Metrics, Management, and Measurement
inferredcites →https://doi.org/10.1109/mdt.2010.7openalex-snapshot
A Survey of Hardware Trojan Taxonomy and Detection
inferredcites →https://doi.org/10.1109/mdt.2012.2196252openalex-snapshot
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution
inferredcites →https://doi.org/10.1109/sp.2007.28openalex-snapshot
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
inferredcites →https://doi.org/10.1109/tdsc.2018.2812183openalex-snapshot
HAL—The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion
inferredcites →https://doi.org/10.1109/tvlsi.2004.825834openalex-snapshot
Scaling trends of on-chip power distribution noise
inferredcites →https://doi.org/10.1145/2133352.2133353openalex-snapshot
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
inferredcites →https://doi.org/10.1145/2228360.2228512openalex-snapshot
Architecture support for accelerator-rich CMPs
inferredcites →https://doi.org/10.1145/2435264.2435283openalex-snapshot
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
inferredcites →https://doi.org/10.1145/274535.274566openalex-snapshot
Analysis, reduction and avoidance of crosstalk on VLSI chips
inferredcites →https://doi.org/10.1145/503048.503072openalex-snapshot
Dynamic power consumption in Virtex™-II FPGA family
inferredcites →https://doi.org/10.1371/journal.pone.0033799openalex-snapshot
Hierarchy Measure for Complex Networks
inferredcites →https://doi.org/10.46586/tches.v2018.i3.44-68openalex-snapshot
FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_10openalex-snapshot
Countermeasures Against Voltage Attacks in Multi-tenant FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_4openalex-snapshot
Remote Physical Attacks on FPGAs at the Electrical Level
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_5openalex-snapshot
Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_6openalex-snapshot
Contention-Based Threats Between Single-Tenant Cloud FPGA Instances
inferred← citeshttps://doi.org/10.1007/s11227-025-07340-5openalex-snapshot
Toward secure program execution in multi-tenant cloud FPGA environments
inferred← citeshttps://doi.org/10.1007/s11704-022-2127-0openalex-snapshot
FPGA sharing in the cloud: a comprehensive analysis
inferred← citeshttps://doi.org/10.1007/s41635-023-00135-1openalex-snapshot
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
inferred← citeshttps://doi.org/10.1016/j.cose.2026.104912openalex-snapshot
Explainable hardware Trojan detection and localization in FPGA Netlists
inferred← citeshttps://doi.org/10.1109/access.2022.3231753openalex-snapshot
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks
inferred← citeshttps://doi.org/10.1109/access.2024.3353134openalex-snapshot
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/asianhost59942.2023.10409460openalex-snapshot
AHD-LAM: A New Mitigation Method against Voltage-Drop Attacks in Multi-tenant FPGAs
inferred← citeshttps://doi.org/10.1109/ats64447.2024.10915413openalex-snapshot
Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586098openalex-snapshot
Classifying Computations on Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132492openalex-snapshot
LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
inferred← citeshttps://doi.org/10.1109/dchpc69296.2026.11517259openalex-snapshot
Evaluating the Impact of Active Wire Fence Placement on Remote Power Side-Channel Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1109/ddecs57882.2023.10138941openalex-snapshot
Active Wire Fences for Multitenant FPGAs
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00055openalex-snapshot
Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
inferred← citeshttps://doi.org/10.1109/ets56758.2023.10173861openalex-snapshot
Criticality Analysis of Ring Oscillators in FPGA Bitstreams *
inferred← citeshttps://doi.org/10.1109/ets61313.2024.10567821openalex-snapshot
Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks*
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00040openalex-snapshot
SoK: Secure FPGA Multi-Tenancy in the Cloud: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00036openalex-snapshot
Trusted Configuration in Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786107openalex-snapshot
Reverse Engineering Neural Network Folding with Remote FPGA Power Analysis
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00060openalex-snapshot
Power Side-Channel Attacks and Defenses for Neural Network Accelerators
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00046openalex-snapshot
Power Wasting Circuits for Cloud FPGA Attacks
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00069openalex-snapshot
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00066openalex-snapshot
Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault Attacks
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00046openalex-snapshot
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545411openalex-snapshot
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643485openalex-snapshot
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00029openalex-snapshot
Cloud FPGA Security with RO-Based Primitives
inferred← citeshttps://doi.org/10.1109/icicm59499.2023.10365938openalex-snapshot
A Case Study on the Internal Mutual Interference of Multitenant FPGA
inferred← citeshttps://doi.org/10.1109/iclad65226.2025.00023openalex-snapshot
A Dataset for LLM-Based Detection of Power-Wasters in Routed FPGA Netlists
inferred← citeshttps://doi.org/10.1109/ipdpsw59300.2023.00025openalex-snapshot
Is Your FPGA Transmitting Secrets: Covert Antennas from Interconnect
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00058openalex-snapshot
New Security Threats on FPGAs: From FPGA Design Tools Perspective
inferred← citeshttps://doi.org/10.1109/isvlsi61997.2024.00151openalex-snapshot
Natural Language Processing Meets Hardware Trojan Detection: Automating Security of FPGAs
inferred← citeshttps://doi.org/10.1109/jproc.2023.3330729openalex-snapshot
A Visionary Look at the Security of Reconfigurable Cloud Computing
inferred← citeshttps://doi.org/10.1109/lats70329.2026.11480311openalex-snapshot
PowerCourt: Formally Judging Benign-Looking Circuits in Multi-Tenant FPGA Environments
inferred← citeshttps://doi.org/10.1109/mdat.2022.3142199openalex-snapshot
Long-Wire Leakage: The Threat of Crosstalk
inferred← citeshttps://doi.org/10.1109/mdat.2022.3151022openalex-snapshot
Remote Fault Attacks in Multitenant Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/paine62042.2024.10792722openalex-snapshot
In-Situ FPGA Fault Injection with Short-Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2024.3443769openalex-snapshot
Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata
inferred← citeshttps://doi.org/10.1109/tcc.2026.3698470openalex-snapshot
Toward FPGA Cloud Security: A Ring Oscillator-Free and Low-Power Attack Circuit
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3550568openalex-snapshot
A Covert and Efficient Attack on FPGA Cloud Based on Adaptive RON
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3604607openalex-snapshot
Design for Assurance: Employing Functional Verification Tools for Thwarting Hardware Trojan Threat in 3PIPs
inferred← citeshttps://doi.org/10.1109/tifs.2021.3106169openalex-snapshot
Stealing Neural Network Structure Through Remote FPGA Side-Channel Analysis
inferred← citeshttps://doi.org/10.1109/tifs.2026.3657612openalex-snapshot
PHANTOM: Power Hammering Attack and Countermeasure on Multi-Tenant ReRAM Compute-in-Memory Accelerators
inferred← citeshttps://doi.org/10.1109/trustcom60117.2023.00259openalex-snapshot
A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
inferred← citeshttps://doi.org/10.1109/tvlsi.2020.3027711openalex-snapshot
Power Distribution Attacks in Multitenant FPGAs
inferred← citeshttps://doi.org/10.1145/3373087.3375322openalex-snapshot
Fingerprinting Cloud FPGA Infrastructures
inferred← citeshttps://doi.org/10.1145/3400302.3415695openalex-snapshot
Information leakage from FPGA routing and logic elements
inferred← citeshttps://doi.org/10.1145/3451236openalex-snapshot
Mitigating Voltage Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1145/3460229openalex-snapshot
Voltage-Based Covert Channels Using FPGAs
inferred← citeshttps://doi.org/10.1145/3498337openalex-snapshot
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
inferred← citeshttps://doi.org/10.1145/3534972openalex-snapshot
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3543622.3573193openalex-snapshot
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters
inferred← citeshttps://doi.org/10.1145/3555048openalex-snapshot
Voltage Sensor Implementations for Remote Power Attacks on FPGAs
inferred← citeshttps://doi.org/10.1145/3620665.3640355openalex-snapshot
Pentimento: Data Remanence in Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3633204openalex-snapshot
On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)
inferred← citeshttps://doi.org/10.1145/3635312openalex-snapshot
Covert-channels in FPGA-enabled SmartSSDs
inferred← citeshttps://doi.org/10.1145/3666092openalex-snapshot
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters
inferred← citeshttps://doi.org/10.1145/3676536.3676843openalex-snapshot
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering
inferred← citeshttps://doi.org/10.1145/3713082.3730385openalex-snapshot
Apiary: An OS for the Modern FPGA
inferred← citeshttps://doi.org/10.1145/3735556openalex-snapshot
Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties
inferred← citeshttps://doi.org/10.1145/3756013openalex-snapshot
S 2 FAM: Signal-slowdown-based Fault Attack Mitigation Method for Secure Multi-tenant FPGA
inferred← citeshttps://doi.org/10.1145/3761809openalex-snapshot
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs
inferred← citeshttps://doi.org/10.1145/3846381openalex-snapshot
Faults that Persist: Fault-Injection Attacks and ASCON-Based Defense in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473938openalex-snapshot
Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473947openalex-snapshot
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474140openalex-snapshot
Remote and Stealthy Fault Attacks on Virtualized FPGAs
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992759openalex-snapshot
Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation
inferred← citeshttps://doi.org/10.3390/cryptography8030036openalex-snapshot
Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs
inferred← citeshttps://doi.org/10.46586/tches.v2020.i3.121-146openalex-snapshot
CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design
inferred← citeshttps://doi.org/10.46586/tches.v2021.i3.441-464openalex-snapshot
Denial-of-Service on FPGA-based Cloud Infrastructures — Attack and Defense
inferred← citeshttps://doi.org/10.46586/tches.v2023.i2.543-567openalex-snapshot
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks
inferred← citeshttps://doi.org/10.48550/arxiv.2005.04867openalex-snapshot
Security of Cloud FPGAs: A Survey
inferred← citeshttps://doi.org/10.48550/arxiv.2009.13914openalex-snapshot
SoK: On the Security Challenges and Risks of Multi-Tenant FPGAs in the Cloud
inferred← citeshttps://doi.org/10.62051/ijcsit.v3n3.38openalex-snapshot
Physical Damage to the Circuit Overview Based on FPGA
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