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FPGAD efender
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4613-2821-6openalex-snapshot
Logic Minimization Algorithms for VLSI Synthesis
inferredcites →https://doi.org/10.1007/978-1-4614-1225-0openalex-snapshot
Partial Reconfiguration on FPGAs : Architectures, Tools and Applications
inferredcites →https://doi.org/10.1007/978-3-319-26408-0openalex-snapshot
FPGAs for Software Programmers
inferredcites →https://doi.org/10.1007/978-3-319-26408-0_1openalex-snapshot
FPGA Versus Software Programming: Why, When, and How?
inferredcites →https://doi.org/10.1007/978-3-540-45146-4_27openalex-snapshot
Private Circuits: Securing Hardware against Probing Attacks
inferredcites →https://doi.org/10.1007/978-3-642-23951-9_3openalex-snapshot
Generic Side-Channel Countermeasures for Reconfigurable Devices
inferredcites →https://doi.org/10.1007/978-981-10-8776-9openalex-snapshot
Advanced HDL Synthesis and SOC Prototyping
inferredcites →https://doi.org/10.1007/s11265-006-0017-6openalex-snapshot
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
inferredcites →https://doi.org/10.1007/s13389-016-0132-7openalex-snapshot
Interdiction in practice—Hardware Trojan against a high-security USB flash drive
inferredcites →https://doi.org/10.1049/el.2019.0163openalex-snapshot
Oscillator without a combinatorial loop and its threat to FPGA in data centre
inferredcites →https://doi.org/10.1109/access.2019.2901949openalex-snapshot
A Comprehensive FPGA Reverse Engineering Tool-Chain: From Bitstream to RTL Code
inferredcites →https://doi.org/10.1109/ems.2016.036openalex-snapshot
High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis
inferredcites →https://doi.org/10.1109/fccm.2012.17openalex-snapshot
Go Ahead: A Partial Reconfiguration Framework
inferredcites →https://doi.org/10.1109/fccm.2018.00016openalex-snapshot
FPGA Side Channel Attacks without Physical Access
inferredcites →https://doi.org/10.1109/fpga.1996openalex-snapshot
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines
inferredcites →https://doi.org/10.1109/fpl.2010.117openalex-snapshot
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
inferredcites →https://doi.org/10.1109/fpl.2012.6339165openalex-snapshot
Bil: A tool-chain for bitstream reverse-engineering
inferredcites →https://doi.org/10.1109/fpl.2013.6645511openalex-snapshot
Should FPGAS abandon the pass-gate?
inferredcites →https://doi.org/10.1109/fpl.2018.00028openalex-snapshot
Resource Elastic Virtualization for FPGAs Using OpenCL
inferredcites →https://doi.org/10.1109/fpl.2019.00017openalex-snapshot
Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs
inferredcites →https://doi.org/10.1109/fpl.2019.00038openalex-snapshot
Characterizing Power Distribution Attacks in Multi-User FPGA Environments
inferredcites →https://doi.org/10.1109/fpl.2019.00039openalex-snapshot
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey
inferredcites →https://doi.org/10.1109/fpl.2019.00081openalex-snapshot
The FOS (FPGA Operating System) Demo
inferredcites →https://doi.org/10.1109/fpl48882.2019openalex-snapshot
2019 29th International Conference on Field Programmable Logic and Applications (FPL)
inferredcites →https://doi.org/10.1109/fpt.2016.7929519openalex-snapshot
Spector: An OpenCL FPGA benchmark suite
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942094openalex-snapshot
Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs
inferredcites →https://doi.org/10.1109/icscs.2009.5412599openalex-snapshot
Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
inferredcites →https://doi.org/10.1109/icscs.2009.5412604openalex-snapshot
Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher
inferredcites →https://doi.org/10.1109/ipdps.2005.380openalex-snapshot
REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
inferredcites →https://doi.org/10.1109/ipdps.2005.435openalex-snapshot
Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium
inferredcites →https://doi.org/10.1109/jproc.2014.2331672openalex-snapshot
FPGA Security: Motivations, Features, and Applications
inferredcites →https://doi.org/10.1109/mcsoc2018.2018.00018openalex-snapshot
IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs
inferredcites →https://doi.org/10.1109/sp.2018.00049openalex-snapshot
FPGA-Based Remote Power Side-Channel Attacks
inferredcites →https://doi.org/10.1109/tc.2016.2646367openalex-snapshot
Bitstream Fault Injections (BiFI)–Automated Fault Attacks Against SRAM-Based FPGAs
inferredcites →https://doi.org/10.1109/tc.2017.2651829openalex-snapshot
GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs
inferredcites →https://doi.org/10.1109/tcad.2015.2399455openalex-snapshot
FPGA Trojans Through Detecting and Weakening of Cryptographic Primitives
inferredcites →https://doi.org/10.1117/12.221340openalex-snapshot
Teramac configurable custom computer
inferredcites →https://doi.org/10.1145/1046192.1046195openalex-snapshot
The Stratix II logic and routing architecture
inferredcites →https://doi.org/10.1145/2133352.2133353openalex-snapshot
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
inferredcites →https://doi.org/10.1145/2435264.2435283openalex-snapshot
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
inferredcites →https://doi.org/10.1145/2678373.2665678openalex-snapshot
A reconfigurable fabric for accelerating large-scale datacenter services
inferredcites →https://doi.org/10.1145/3240765.3240841openalex-snapshot
Remote inter-chip power analysis side-channel attacks at board-level
inferredcites →https://doi.org/10.1145/3328222openalex-snapshot
Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
inferredcites →https://doi.org/10.1145/3337801.3337814openalex-snapshot
Implementation of FPGA Building Platform as a Cloud Service
inferredcites →https://doi.org/10.1145/774572openalex-snapshot
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD '02
inferredcites →https://doi.org/10.1201/9780429399602-7openalex-snapshot
A Novel Framework for Utilising Multi-FPGAs in HPC Systems
inferredcites →https://doi.org/10.23919/date.2017.7927114openalex-snapshot
BITMAN: A tool and API for FPGA bitstream manipulations
inferredcites →https://doi.org/10.23919/date.2018.8342177openalex-snapshot
An inside job: Remote power analysis attacks on FPGAs
inferredcites →https://doi.org/10.23919/fpl.2017.8056817openalex-snapshot
A security library for FPGA interlays
inferredcites →https://doi.org/10.23919/fpl.2017.8056840openalex-snapshot
Voltage drop-based fault attacks on FPGAs using valid bitstreams
inferredcites →https://doi.org/10.46586/tches.v2018.i3.44-68openalex-snapshot
FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_1openalex-snapshot
Authentication and Confidentiality in FPGA-Based Clouds
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_10openalex-snapshot
Countermeasures Against Voltage Attacks in Multi-tenant FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_11openalex-snapshot
Programmable RO (PRO): A Multipurpose Countermeasure Against Side-Channel and Fault Injection Attack
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_4openalex-snapshot
Remote Physical Attacks on FPGAs at the Electrical Level
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_5openalex-snapshot
Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_6openalex-snapshot
Contention-Based Threats Between Single-Tenant Cloud FPGA Instances
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_7openalex-snapshot
Cross-board Power-Based FPGA, CPU, and GPU Covert Channels
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_9openalex-snapshot
Fingerprinting and Mapping Cloud FPGA Infrastructures
inferred← citeshttps://doi.org/10.1007/978-3-031-55673-9_14openalex-snapshot
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices
inferred← citeshttps://doi.org/10.1007/978-3-031-87995-1_6openalex-snapshot
ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives
inferred← citeshttps://doi.org/10.1007/s11227-025-07340-5openalex-snapshot
Toward secure program execution in multi-tenant cloud FPGA environments
inferred← citeshttps://doi.org/10.1007/s41635-023-00135-1openalex-snapshot
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
inferred← citeshttps://doi.org/10.1007/s41635-024-00148-4openalex-snapshot
Enabling Secure and Efficient Sharing of Accelerators in Expeditionary Systems
inferred← citeshttps://doi.org/10.1007/s41635-024-00155-5openalex-snapshot
High-Confidence Remote Power Analysis on Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1016/j.cose.2026.104912openalex-snapshot
Explainable hardware Trojan detection and localization in FPGA Netlists
inferred← citeshttps://doi.org/10.1109/access.2022.3231753openalex-snapshot
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks
inferred← citeshttps://doi.org/10.1109/access.2024.3353134openalex-snapshot
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/ats59501.2023.10318003openalex-snapshot
A Covert Attack Method Against FPGA Clouds
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586262openalex-snapshot
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00055openalex-snapshot
Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
inferred← citeshttps://doi.org/10.1109/ets54262.2022.9810438openalex-snapshot
Detection of Malicious FPGA Bitstreams using CNN-Based Learning
inferred← citeshttps://doi.org/10.1109/ets56758.2023.10173861openalex-snapshot
Criticality Analysis of Ring Oscillators in FPGA Bitstreams *
inferred← citeshttps://doi.org/10.1109/ets56758.2023.10174155openalex-snapshot
BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering
inferred← citeshttps://doi.org/10.1109/ets61313.2024.10567821openalex-snapshot
Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks*
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00040openalex-snapshot
SoK: Secure FPGA Multi-Tenancy in the Cloud: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1109/eurospw59978.2023.00035openalex-snapshot
Combined Internal Attacks on SoC-FPGAs: Breaking AES with Remote Power Analysis and Frequency-based Covert Channels
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00035openalex-snapshot
Cloud FPGA Cartography using PCIe Contention
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00036openalex-snapshot
Trusted Configuration in Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00060openalex-snapshot
Power Side-Channel Attacks and Defenses for Neural Network Accelerators
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00069openalex-snapshot
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00074openalex-snapshot
Demo: A Closer Look at Malicious Bitstreams
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00039openalex-snapshot
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00066openalex-snapshot
Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault Attacks
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00046openalex-snapshot
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545353openalex-snapshot
A Lightweight Non-Oscillatory Delay-Sensor for Remote Power Analysis
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545411openalex-snapshot
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643485openalex-snapshot
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323545openalex-snapshot
PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00029openalex-snapshot
Cloud FPGA Security with RO-Based Primitives
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974230openalex-snapshot
A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00007openalex-snapshot
A Tenant Side Compilation Solution for Cloud FPGA Deployment
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00021openalex-snapshot
Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison
inferred← citeshttps://doi.org/10.1109/icm66518.2025.11322515openalex-snapshot
Applying AI for and on Hardware: Cross-Layer Approaches for Security and Efficiency
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00059openalex-snapshot
A Survey of Recent Attacks and Mitigation on FPGA Systems
inferred← citeshttps://doi.org/10.1109/jproc.2023.3330729openalex-snapshot
A Visionary Look at the Security of Reconfigurable Cloud Computing
inferred← citeshttps://doi.org/10.1109/lats70329.2026.11480311openalex-snapshot
PowerCourt: Formally Judging Benign-Looking Circuits in Multi-Tenant FPGA Environments
inferred← citeshttps://doi.org/10.1109/mdat.2022.3142199openalex-snapshot
Long-Wire Leakage: The Threat of Crosstalk
inferred← citeshttps://doi.org/10.1109/mdat.2022.3151022openalex-snapshot
Remote Fault Attacks in Multitenant Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/mdat.2024.3448371openalex-snapshot
Remote Power Side- Channel Attacks on FPGAs
inferred← citeshttps://doi.org/10.1109/paine54418.2021.9707700openalex-snapshot
Bitstream Reverse Engineering of Microsemi’s VersaTile-based FPGAs
inferred← citeshttps://doi.org/10.1109/seed61283.2024.00011openalex-snapshot
Extending FPGA Information Leaks with Trojan Phantom Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2022.3190771openalex-snapshot
Learning Malicious Circuits in FPGA Bitstreams
inferred← citeshttps://doi.org/10.1109/tcad.2023.3272268openalex-snapshot
Diagnosis of Malicious Bitstreams in Cloud Computing FPGAs
inferred← citeshttps://doi.org/10.1109/tcad.2024.3443769openalex-snapshot
Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata
inferred← citeshttps://doi.org/10.1109/tcc.2026.3698470openalex-snapshot
Toward FPGA Cloud Security: A Ring Oscillator-Free and Low-Power Attack Circuit
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3435841openalex-snapshot
Power and Frequency Intrinsic Channels on gem5
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3421323openalex-snapshot
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3550568openalex-snapshot
A Covert and Efficient Attack on FPGA Cloud Based on Adaptive RON
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3604607openalex-snapshot
Design for Assurance: Employing Functional Verification Tools for Thwarting Hardware Trojan Threat in 3PIPs
inferred← citeshttps://doi.org/10.1109/tdsc.2026.3685885openalex-snapshot
SecTEND: Secure Deployment of Heterogeneous Applications for Multi-Tenant FPGA-Based Platforms
inferred← citeshttps://doi.org/10.1109/tifs.2021.3106169openalex-snapshot
Stealing Neural Network Structure Through Remote FPGA Side-Channel Analysis
inferred← citeshttps://doi.org/10.1109/vlsi-soc62099.2024.10767802openalex-snapshot
Lightweight Active Fences for FPGAs
inferred← citeshttps://doi.org/10.1145/3460229openalex-snapshot
Voltage-Based Covert Channels Using FPGAs
inferred← citeshttps://doi.org/10.1145/3491214openalex-snapshot
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA
inferred← citeshttps://doi.org/10.1145/3498337openalex-snapshot
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
inferred← citeshttps://doi.org/10.1145/3534972openalex-snapshot
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3555048openalex-snapshot
Voltage Sensor Implementations for Remote Power Attacks on FPGAs
inferred← citeshttps://doi.org/10.1145/3566097.3568346openalex-snapshot
Detection and Classification of Malicious Bitstreams for FPGAs in Cloud Computing
inferred← citeshttps://doi.org/10.1145/3633204openalex-snapshot
On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)
inferred← citeshttps://doi.org/10.1145/3635312openalex-snapshot
Covert-channels in FPGA-enabled SmartSSDs
inferred← citeshttps://doi.org/10.1145/3676536.3676843openalex-snapshot
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering
inferred← citeshttps://doi.org/10.1145/3676641.3716012openalex-snapshot
PhasePrint: Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime
inferred← citeshttps://doi.org/10.1145/3702324openalex-snapshot
Watch Out for the Inherent Vulnerabilities in Developing Multi-tenant Cloud-FPGA: Communication Protocols
inferred← citeshttps://doi.org/10.1145/3706628.3708826openalex-snapshot
CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers
inferred← citeshttps://doi.org/10.1145/3713078openalex-snapshot
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy
inferred← citeshttps://doi.org/10.1145/3735556openalex-snapshot
Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties
inferred← citeshttps://doi.org/10.1145/3761809openalex-snapshot
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs
inferred← citeshttps://doi.org/10.1145/3846381openalex-snapshot
Faults that Persist: Fault-Injection Attacks and ASCON-Based Defense in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473938openalex-snapshot
Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473947openalex-snapshot
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474140openalex-snapshot
Remote and Stealthy Fault Attacks on Virtualized FPGAs
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774663openalex-snapshot
FPGA-to-CPU Undervolting Attacks
inferred← citeshttps://doi.org/10.23919/date56975.2023.10136956openalex-snapshot
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992759openalex-snapshot
Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation
inferred← citeshttps://doi.org/10.3390/agronomy13040987openalex-snapshot
Detection of Male and Female Litchi Flowers Using YOLO-HPFD Multi-Teacher Feature Distillation and FPGA-Embedded Platform
inferred← citeshttps://doi.org/10.3390/jlpea12030048openalex-snapshot
Time- and Amplitude-Controlled Power Noise Generator against SPA Attacks for FPGA-Based IoT Devices
inferred← citeshttps://doi.org/10.48550/arxiv.2009.13914openalex-snapshot
SoK: On the Security Challenges and Risks of Multi-Tenant FPGAs in the Cloud
inferred← citeshttps://doi.org/10.62051/ijcsit.v3n3.38openalex-snapshot
Physical Damage to the Circuit Overview Based on FPGA
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