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Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

https://doi.org/10.1145/3498683
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-31424-7_36openalex-snapshot
An Axiomatic Memory Model for POWER Multiprocessors
inferredcites →https://doi.org/10.1007/978-3-642-37036-6_29openalex-snapshot
Checking and Enforcing Robustness against TSO
inferredcites →https://doi.org/10.1007/978-3-662-46669-8_13openalex-snapshot
The Best of Both Worlds: Trading Efficiency and Optimality in Fence Insertion for TSO
inferredcites →https://doi.org/10.1007/978-3-662-46681-0_28openalex-snapshot
Stateless Model Checking for TSO and PSO
inferredcites →https://doi.org/10.1007/978-3-662-47666-6_25openalex-snapshot
Owicki-Gries Reasoning for Weak Memory Models
inferredcites →https://doi.org/10.1007/978-3-662-48653-5_41openalex-snapshot
Hardware Transactions in Nonvolatile Memory
inferredcites →https://doi.org/10.1007/978-3-662-49122-5_20openalex-snapshot
A Program Logic for C11 Memory Fences
inferredcites →https://doi.org/10.1007/978-3-662-54434-1_17openalex-snapshot
Tackling Real-Life Relaxed Concurrency with FSL++
inferredcites →https://doi.org/10.1109/fccm.2018.00035openalex-snapshot
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments
inferredcites →https://doi.org/10.1109/hpca51647.2021.00019openalex-snapshot
BBB: Simplifying Persistent Programming using Battery-Backed Buffers
inferredcites →https://doi.org/10.1109/isca45697.2020.00060openalex-snapshot
Relaxed Persist Ordering Using Strand Persistency
inferredcites →https://doi.org/10.1109/nvmsa.2018.00015openalex-snapshot
Empirical Study of Transactional Management for Persistent Memory
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1145/1040305.1040336openalex-snapshot
The Java memory model
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1785414.1785443openalex-snapshot
x86-TSO
inferredcites →https://doi.org/10.1145/1926385.1926394openalex-snapshot
Mathematizing C++ concurrency
inferredcites →https://doi.org/10.1145/1993316.1993520openalex-snapshot
Understanding POWER multiprocessors
inferredcites →https://doi.org/10.1145/2509136.2509532openalex-snapshot
Relaxed separation logic
inferredcites →https://doi.org/10.1145/2627752openalex-snapshot
Herding Cats
inferredcites →https://doi.org/10.1145/2714064.2660243openalex-snapshot
GPS
inferredcites →https://doi.org/10.1145/2837614.2837615openalex-snapshot
Modelling the ARMv8 architecture, operationally: concurrency and ISA
inferredcites →https://doi.org/10.1145/2837614.2837616openalex-snapshot
A concurrency semantics for relaxed atomics that permits optimisation and avoids thin-air executions
inferredcites →https://doi.org/10.1145/2914770.2837643openalex-snapshot
Taming release-acquire consistency
inferredcites →https://doi.org/10.1145/2954679.2872381openalex-snapshot
High-Performance Transactions for Persistent Memories
inferredcites →https://doi.org/10.1145/2983990.2983997openalex-snapshot
An operational semantics for C/C++11 concurrency
inferredcites →https://doi.org/10.1145/3062341.3062352openalex-snapshot
Repairing sequential consistency in C/C++11
inferredcites →https://doi.org/10.1145/3079856.3080229openalex-snapshot
Language-level persistency
inferredcites →https://doi.org/10.1145/3093333.3009850openalex-snapshot
A promising semantics for relaxed-memory concurrency
inferredcites →https://doi.org/10.1145/3158107openalex-snapshot
Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8
inferredcites →https://doi.org/10.1145/3192366.3192367openalex-snapshot
Persistency for synchronization-free regions
inferredcites →https://doi.org/10.1145/3276507openalex-snapshot
Persistence semantics for weak memory: integrating epoch persistency with the TSO memory model
inferredcites →https://doi.org/10.1145/3290382openalex-snapshot
Bridging the gap between programming languages and hardware weak memory models
inferredcites →https://doi.org/10.1145/3290383openalex-snapshot
Grounding thin-air reads with event structures
inferredcites →https://doi.org/10.1145/3296957.3177156openalex-snapshot
Frightening Small Children and Disconcerting Grown-ups
inferredcites →https://doi.org/10.1145/3314221.3314609openalex-snapshot
Model checking for weakly consistent libraries
inferredcites →https://doi.org/10.1145/3360561openalex-snapshot
Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models
inferredcites →https://doi.org/10.1145/3360568openalex-snapshot
A formalization of Java’s concurrent access modes
inferredcites →https://doi.org/10.1145/3360599openalex-snapshot
Effective lock handling in stateless model checking
inferredcites →https://doi.org/10.1145/3371079openalex-snapshot
Persistency semantics of the Intel-x86 architecture
inferredcites →https://doi.org/10.1145/3373376.3378480openalex-snapshot
HMC
inferredcites →https://doi.org/10.1145/3385412.3385966openalex-snapshot
Decidable verification under a causally consistent shared memory
inferredcites →https://doi.org/10.1145/3385412.3386010openalex-snapshot
Promising 2.0: global optimizations in relaxed memory concurrency
inferredcites →https://doi.org/10.1145/3428219openalex-snapshot
Persistent Owicki-Gries reasoning: a program logic for reasoning about persistent programs on Intel-x86
inferredcites →https://doi.org/10.1145/3434324openalex-snapshot
PerSeVerE: persistency semantics for verification under ext4
inferredcites →https://doi.org/10.1145/3434328openalex-snapshot
Taming x86-TSO persistency
inferredcites →https://doi.org/10.1145/3434337openalex-snapshot
Deciding reachability under persistent x86-TSO
inferredcites →https://doi.org/10.1145/3453483.3454027openalex-snapshot
Revamping hardware persistency models: view-based and axiomatic persistency models for Intel-x86 and Armv8
inferredcites →https://doi.org/10.1145/3458926openalex-snapshot
Armed Cats
inferredcites →https://doi.org/10.1145/3462312openalex-snapshot
X86_64 Memory Type Tests.
inferredcites →https://doi.org/10.1145/42190.42277openalex-snapshot
Efficient and correct execution of parallel programs that share memory
inferredcites →https://doi.org/10.4230/darts.6.2.4openalex-snapshot
Reconciling Event Structures with Modern Multiprocessors (Artifact)
inferredcites →https://doi.org/10.4230/lipics.ecoop.2017.17openalex-snapshot
Strong Logic for Weak Memory: Reasoning About Release-Acquire Consistency in Iris
inferredcites →https://doi.org/10.4230/lipics.ecoop.2017.22openalex-snapshot
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
inferredcites →https://doi.org/10.4230/lipics.ecoop.2020.11openalex-snapshot
Owicki-Gries Reasoning for C11 RAR

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-99336-8_9openalex-snapshot
View-Based Owicki–Gries Reasoning for Persistent x86-TSO
inferred← citeshttps://doi.org/10.1007/978-3-031-25803-9_6openalex-snapshot
SMT-Based Verification of Persistency Invariants of Px86 Programs
inferred← citeshttps://doi.org/10.1007/978-3-031-57267-8openalex-snapshot
Programming Languages and Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-57267-8_6openalex-snapshot
Intel PMDK Transactions: Specification, Validation and Concurrency
inferred← citeshttps://doi.org/10.1007/978-3-031-57267-8_8openalex-snapshot
Specifying and Verifying Persistent Libraries
inferred← citeshttps://doi.org/10.1007/978-3-031-91118-7_3openalex-snapshot
Sufficient Conditions for Robustness of RDMA Programs
inferred← citeshttps://doi.org/10.1007/978-3-031-98668-0_18openalex-snapshot
Structural Operational Semantics for Functional and Security Verification of Pipelined Processors
inferred← citeshttps://doi.org/10.1007/s10703-024-00462-1openalex-snapshot
A verified durable transactional mutex lock for persistent x86-TSO
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132607openalex-snapshot
CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer Systems
inferred← citeshttps://doi.org/10.1109/icde65706.2026.00060openalex-snapshot
Reconfiguring Scalable Hashing with Persistent CPU Caches
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00025openalex-snapshot
LightWSP: Whole-System Persistence on the Cheap
inferred← citeshttps://doi.org/10.1109/tpds.2025.3576438openalex-snapshot
SSS-DIMM: Removing Redundant Data Movement in Trusted DIMM-Based Near-Memory-Processing Kernel Offloading via Secure Space Sharing
inferred← citeshttps://doi.org/10.1145/3519939.3523434openalex-snapshot
Islaris: verification of machine code against authoritative ISA semantics
inferred← citeshttps://doi.org/10.1145/3639476openalex-snapshot
Proceedings of the 2024 ACM/IEEE 44th International Conference on Software Engineering: New Ideas and Emerging Results
inferred← citeshttps://doi.org/10.1145/3656425openalex-snapshot
Verification under Intel-x86 with Persistency
inferred← citeshttps://doi.org/10.1145/3669940.3707269openalex-snapshot
Robustness Verification for Checking Crash Consistency of Non-volatile Memory
inferred← citeshttps://doi.org/10.1145/3689031.3696097openalex-snapshot
Pre-Stores: Proactive Software-guided Movement of Data Down the Memory Hierarchy
inferred← citeshttps://doi.org/10.1145/3689749openalex-snapshot
Extending the C/C++ Memory Model with Inline Assembly
inferred← citeshttps://doi.org/10.1145/3689781openalex-snapshot
Semantics of Remote Direct Memory Access: Operational and Declarative Models of RDMA on TSO Architectures
inferred← citeshttps://doi.org/10.1145/3713082.3730389openalex-snapshot
Stop Taking the Scenic Route: the Shortest Distance Between the CPU and the NIC is MMIO
inferred← citeshttps://doi.org/10.1145/3776650openalex-snapshot
ArchSem: Reusable Rigorous Semantics of Relaxed Architectures
inferred← citeshttps://doi.org/10.1145/3776680openalex-snapshot
Parametrised Verification of Intel-x86 Programs
inferred← citeshttps://doi.org/10.1145/3797905.3800523openalex-snapshot
Anchoring Whole-System Persistence and Resilience in CXL
inferred← citeshttps://doi.org/10.1145/3839465openalex-snapshot
A Formal Account of the Wasm 3.0 Concurrency Model
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