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Estimating cache misses and locality using stack distances

https://doi.org/10.1145/782814.782836
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-44570-6_5openalex-snapshot
Adaptively Mapping Code in an Intelligent Memory Architecture
inferredcites →https://doi.org/10.1007/3-540-44905-1_23openalex-snapshot
Compile-Time Based Performance Prediction
inferredcites →https://doi.org/10.1007/bf02700049openalex-snapshot
Region-based compilation: Introduction, motivation, and initial experience
inferredcites →https://doi.org/10.1007/bfb0031655openalex-snapshot
Estimating cache performance for sequential and data parallel programs
inferredcites →https://doi.org/10.1007/bfb0038674openalex-snapshot
On estimating and enhancing cache effectiveness
inferredcites →https://doi.org/10.1016/0743-7315(88)90014-7openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/12.40842openalex-snapshot
Evaluating associativity in CPU caches
inferredcites →https://doi.org/10.1109/2.546612openalex-snapshot
Parallel programming with Polaris
inferredcites →https://doi.org/10.1109/71.577265openalex-snapshot
Fusion of loops for parallelism and locality
inferredcites →https://doi.org/10.1109/71.706049openalex-snapshot
A compiler optimization algorithm for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/fmpc.1999.750595openalex-snapshot
Delphi: an integrated, language-directed performance prediction, measurement and analysis environment
inferredcites →https://doi.org/10.1109/hpca.2001.903257openalex-snapshot
Automatically mapping code on an intelligent memory architecture
inferredcites →https://doi.org/10.1109/hpca.2002.995708openalex-snapshot
Let's study whole-program cache behaviour analytically
inferredcites →https://doi.org/10.1109/micro.1995.476823openalex-snapshot
Region-based compilation: an introduction and motivation
inferredcites →https://doi.org/10.1109/tse.1978.231482openalex-snapshot
A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/207110.207162openalex-snapshot
Tile size selection using cache organization and data layout
inferredcites →https://doi.org/10.1145/258915.258946openalex-snapshot
Data-centric multi-level blocking
inferredcites →https://doi.org/10.1145/2591635.2667179openalex-snapshot
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests
inferredcites →https://doi.org/10.1145/277650.277664openalex-snapshot
Simplification of array access patterns for compiler optimizations
inferredcites →https://doi.org/10.1145/291069.291051openalex-snapshot
Precise miss analysis for program transformations with caches of arbitrary associativity
inferredcites →https://doi.org/10.1145/335231.335245openalex-snapshot
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests
inferredcites →https://doi.org/10.1145/349299.349322openalex-snapshot
Compiler analysis of irregular memory accesses
inferredcites →https://doi.org/10.1145/378795.378859openalex-snapshot
Exact analysis of the cache behavior of nested loops
inferredcites →https://doi.org/10.1145/509705.509708openalex-snapshot
Efficient and precise array access analysis
inferredcites →https://doi.org/10.1145/76263.76337openalex-snapshot
More iteration space tiling
inferredcites →https://doi.org/10.1145/773039.773043openalex-snapshot
Calculating stack distances efficiently
inferredcites →https://doi.org/10.1145/773146.773043openalex-snapshot
Calculating stack distances efficiently
inferredcites →https://doi.org/10.1145/780822.781140openalex-snapshot
A comparison of empirical and model-driven optimization
inferredcites →https://doi.org/10.1145/781131.781140openalex-snapshot
A comparison of empirical and model-driven optimization
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies
inferredcites →https://doi.org/10.5555/266800.266812openalex-snapshot
Tuning compiler optimizations for simultaneous multithreading
inferredcites →https://doi.org/10.5555/509058.509096openalex-snapshot
Automatically Tuned Linear Algebra Software

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11532378_5openalex-snapshot
Phase-Based Miss Rate Prediction Across Program Inputs
inferred← citeshttps://doi.org/10.1007/11688839_4openalex-snapshot
Path-Based Reuse Distance Analysis
inferred← citeshttps://doi.org/10.1007/11777830_6openalex-snapshot
Working Set Characterization of Applications with an Efficient LRU Algorithm
inferred← citeshttps://doi.org/10.1007/11859802_58openalex-snapshot
Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture
inferred← citeshttps://doi.org/10.1007/11945918_55openalex-snapshot
A Study on the Locality Behavior of Minimum Spanning Tree Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-030-16949-7_9openalex-snapshot
A Fast Joint Application-Architecture Exploration Platform for Heterogeneous Systems
inferred← citeshttps://doi.org/10.1007/978-3-030-72789-5_7openalex-snapshot
CLAM: Compiler Leasing of Accelerator Memory
inferred← citeshttps://doi.org/10.1007/978-3-540-39707-6_5openalex-snapshot
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-89740-8_15openalex-snapshot
P-OPT: Program-Directed Optimal Cache Management
inferred← citeshttps://doi.org/10.1007/978-3-642-19861-8_15openalex-snapshot
Practical Loop Transformations for Tensor Contraction Expressions on Multi-level Memory Hierarchies
inferred← citeshttps://doi.org/10.1007/978-3-642-21878-1_13openalex-snapshot
A Work Stealing Scheduler for Parallel Loops on Shared Cache Multicores
inferred← citeshttps://doi.org/10.1007/s00607-016-0535-4openalex-snapshot
A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details
inferred← citeshttps://doi.org/10.1007/s11227-021-03949-4openalex-snapshot
PPT-Multicore: performance prediction of OpenMP applications using reuse profiles and analytical modeling
inferred← citeshttps://doi.org/10.1007/s11390-014-1460-7openalex-snapshot
Performance Metrics and Models for Shared Cache
inferred← citeshttps://doi.org/10.1016/j.cl.2015.01.003openalex-snapshot
A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
inferred← citeshttps://doi.org/10.1016/j.ins.2020.03.078openalex-snapshot
Novel fairness-aware co-scheduling for shared cache contention game on chip multiprocessors
inferred← citeshttps://doi.org/10.1016/j.jpdc.2007.01.010openalex-snapshot
Predicting locality phases for dynamic memory optimization
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.01.010openalex-snapshot
Locality principle revisited: A probability-based quantitative approach
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.02.005openalex-snapshot
An artificial neural network model of LRU-cache misses on out-of-order embedded processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.10.001openalex-snapshot
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses
inferred← citeshttps://doi.org/10.1016/j.parco.2012.11.003openalex-snapshot
Accurate prediction of the behavior of multithreaded applications in shared caches
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.10.002openalex-snapshot
Stack filter: Reducing L1 data cache power consumption
inferred← citeshttps://doi.org/10.1016/j.sysarc.2014.05.003openalex-snapshot
Cache-based high-level simulation of microthreaded many-core architectures
inferred← citeshttps://doi.org/10.1109/access.2022.3180327openalex-snapshot
Efficient Stack Distance Approximation Based on Workload Characteristics
inferred← citeshttps://doi.org/10.1109/access.2025.3589802openalex-snapshot
MLCRP: ML-Based GPU Cache Performance Modeling Featured With Reuse Profiles
inferred← citeshttps://doi.org/10.1109/cgo.2013.6495008openalex-snapshot
Defensive loop tiling for shared cache
inferred← citeshttps://doi.org/10.1109/cluster.2017.77openalex-snapshot
AMM: Scalable Memory Reuse Model to Predict the Performance of Physics Codes
inferred← citeshttps://doi.org/10.1109/cluster.2019.8891025openalex-snapshot
Rapidly Measuring Loop Footprints
inferred← citeshttps://doi.org/10.1109/fpl.2019.00049openalex-snapshot
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses
inferred← citeshttps://doi.org/10.1109/fpt.2010.5681447openalex-snapshot
A configurable framework for investigating workload execution
inferred← citeshttps://doi.org/10.1109/hipc.2012.6507475openalex-snapshot
GMProf: A low-overhead, fine-grained profiling approach for GPU programs
inferred← citeshttps://doi.org/10.1109/hipc.2018.00042openalex-snapshot
A Performance Prediction Framework for Irregular Applications
inferred← citeshttps://doi.org/10.1109/hpca.2017.11openalex-snapshot
Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance
inferred← citeshttps://doi.org/10.1109/hpca.2018.00065openalex-snapshot
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures
inferred← citeshttps://doi.org/10.1109/hpca.2019.00056openalex-snapshot
Featherlight Reuse-Distance Measurement
inferred← citeshttps://doi.org/10.1109/hpcsim.2014.6903790openalex-snapshot
A benchmark-based performance model for memory-bound HPC applications
inferred← citeshttps://doi.org/10.1109/iccsnt.2011.6182032openalex-snapshot
Utility-based dynamic cache resizing
inferred← citeshttps://doi.org/10.1109/icde53745.2022.00178openalex-snapshot
Subspace Embedding Based New Paper Recommendation
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00030openalex-snapshot
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA
inferred← citeshttps://doi.org/10.1109/icmla.2018.00162openalex-snapshot
Applying Supervised Learning to the Static Prediction of Locality-Pattern Complexity in Scientific Code
inferred← citeshttps://doi.org/10.1109/icpads.2009.122openalex-snapshot
When Misses Differ: Investigating Impact of Cache Misses on Observed Performance
inferred← citeshttps://doi.org/10.1109/icpp.2010.43openalex-snapshot
Characterizing the Relation Between Apex-Map Synthetic Probes and Reuse Distance Distributions
inferred← citeshttps://doi.org/10.1109/icpp.2012.40openalex-snapshot
Modeling the Locality in Graph Traversals
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289241openalex-snapshot
Instruction-based reuse-distance prediction for effective cache management
inferred← citeshttps://doi.org/10.1109/ipccc47392.2019.8958760openalex-snapshot
GPUs Cache Performance Estimation using Reuse Distance Analysis
inferred← citeshttps://doi.org/10.1109/ipdps.2005.134openalex-snapshot
Cache Miss Characterization and Data Locality Optimization for Imperfectly Nested Loops on Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370508openalex-snapshot
Supporting Quality of Service in High-Performance Servers
inferred← citeshttps://doi.org/10.1109/ipdps.2011.393openalex-snapshot
Optimizing Large-Scale Graph Analysis on a Multi-threaded, Multi-core Platform
inferred← citeshttps://doi.org/10.1109/ipdps.2012.46openalex-snapshot
Optimizing Large-scale Graph Analysis on Multithreaded, Multicore Platforms
inferred← citeshttps://doi.org/10.1109/ipdps.2012.93openalex-snapshot
Locality Principle Revisited: A Probability-Based Quantitative Approach
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.49openalex-snapshot
CHiP: A Profiler to Measure the Effect of Cache Contention on Scalability
inferred← citeshttps://doi.org/10.1109/ispass.2006.1620793openalex-snapshot
A statistical multiprocessor cache model
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557142openalex-snapshot
XAMP: An eXtensible Analytical Model Platform
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557169openalex-snapshot
Pinpointing data locality bottlenecks with low overhead
inferred← citeshttps://doi.org/10.1109/ispass.2014.6844465openalex-snapshot
Modeling cache coherence misses on multicores
inferred← citeshttps://doi.org/10.1109/ispass48437.2020.00047openalex-snapshot
Rapid Memory Footprint Access Diagnostics
inferred← citeshttps://doi.org/10.1109/isqed.2015.7085411openalex-snapshot
Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures
inferred← citeshttps://doi.org/10.1109/les.2019.2910305openalex-snapshot
AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations
inferred← citeshttps://doi.org/10.1109/llvm-hpc.2014.6openalex-snapshot
Architecture-Independent Modeling of Intra-Node Data Movement
inferred← citeshttps://doi.org/10.1109/mascot.2009.5366821openalex-snapshot
Timing penalties associated with cache sharing
inferred← citeshttps://doi.org/10.1109/memcod.2008.4547695openalex-snapshot
Estimating the Performance of Cache Replacement Policies
inferred← citeshttps://doi.org/10.1109/micro.2007.11openalex-snapshot
Penelope: The NBTI-Aware Processor
inferred← citeshttps://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00022openalex-snapshot
HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
inferred← citeshttps://doi.org/10.1109/pact65351.2025.00021openalex-snapshot
Cache Miss Curve Analysis via Cardinality Domain
inferred← citeshttps://doi.org/10.1109/pdgc.2012.6449844openalex-snapshot
Reducing conflict misses using fraction associative mapping
inferred← citeshttps://doi.org/10.1109/rtss.2010.8openalex-snapshot
A More Precise Abstract Domain for Multi-level Caches for Tighter WCET Analysis
inferred← citeshttps://doi.org/10.1109/rtss59052.2023.00029openalex-snapshot
Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis
inferred← citeshttps://doi.org/10.1109/sbac-pad.2004.22openalex-snapshot
Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement
inferred← citeshttps://doi.org/10.1109/sc.2004.3openalex-snapshot
A Geometric Programming Framework for Optimal Multi-Level Tiling
inferred← citeshttps://doi.org/10.1109/spin48934.2020.9070898openalex-snapshot
CPU Performance Modeling through Analysis of Primitive Operations
inferred← citeshttps://doi.org/10.1109/tc.2007.50openalex-snapshot
Miss Rate Prediction Across Program Inputs and Cache Configurations
inferred← citeshttps://doi.org/10.1109/tc.2017.2723878openalex-snapshot
Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache
inferred← citeshttps://doi.org/10.1109/tc.2019.2906597openalex-snapshot
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories
inferred← citeshttps://doi.org/10.1109/tc.2024.3416747openalex-snapshot
CBANA: A Lightweight, Efficient, and Flexible Cache Behavior Analysis Framework
inferred← citeshttps://doi.org/10.1109/tcad.2016.2582872openalex-snapshot
Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM
inferred← citeshttps://doi.org/10.1109/tkde.2020.3006446openalex-snapshot
Exploiting Data Skew for Improved Query Performance
inferred← citeshttps://doi.org/10.1109/tnet.2014.2306060openalex-snapshot
The Bloom Paradox: When Not to Use a Bloom Filter
inferred← citeshttps://doi.org/10.1109/tpds.2014.2306411openalex-snapshot
FPS: A Fair-Progress Process Scheduling Policy on Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2017.2689010openalex-snapshot
NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2019.2896633openalex-snapshot
Analytical Derivation of Concurrent Reuse Distance Profile for Multi-Threaded Application Running on Chip Multi-Processor
inferred← citeshttps://doi.org/10.1145/1064212.1064232openalex-snapshot
Fast data-locality profiling of native execution
inferred← citeshttps://doi.org/10.1145/1071690.1064232openalex-snapshot
Fast data-locality profiling of native execution
inferred← citeshttps://doi.org/10.1145/1140103.1140304openalex-snapshot
An analytical model for cache replacement policy performance
inferred← citeshttps://doi.org/10.1145/1140277.1140304openalex-snapshot
An analytical model for cache replacement policy performance
inferred← citeshttps://doi.org/10.1145/1183401.1183440openalex-snapshot
Feedback-directed memory disambiguation through store distance analysis
inferred← citeshttps://doi.org/10.1145/1366110.1366129openalex-snapshot
A table-based method for single-pass cache optimization
inferred← citeshttps://doi.org/10.1145/1454115.1454130openalex-snapshot
Characterizing and modeling the behavior of context switch misses
inferred← citeshttps://doi.org/10.1145/1529282.1529722openalex-snapshot
Exploiting stack distance to estimate worst-case data cache performance
inferred← citeshttps://doi.org/10.1145/1552309.1552310openalex-snapshot
Program locality analysis using reuse distance
inferred← citeshttps://doi.org/10.1145/1810085.1810125openalex-snapshot
Static reuse distances for locality-based optimizations in MATLAB
inferred← citeshttps://doi.org/10.1145/1880043.1880048openalex-snapshot
Understanding the behavior and implications of context switch misses
inferred← citeshttps://doi.org/10.1145/1941553.1941567openalex-snapshot
All-window profiling and composable models of cache sharing
inferred← citeshttps://doi.org/10.1145/1993478.1993485openalex-snapshot
On the theory and potential of LRU-MRU collaborative cache management
inferred← citeshttps://doi.org/10.1145/2038037.1941567openalex-snapshot
All-window profiling and composable models of cache sharing
inferred← citeshttps://doi.org/10.1145/2076022.1993485openalex-snapshot
On the theory and potential of LRU-MRU collaborative cache management
inferred← citeshttps://doi.org/10.1145/2212908.2212936openalex-snapshot
Reuse distance based performance modeling and workload mapping
inferred← citeshttps://doi.org/10.1145/2254756.2254792openalex-snapshot
Providing fairness on shared-memory multiprocessors via process scheduling
inferred← citeshttps://doi.org/10.1145/2258996.2259012openalex-snapshot
A generalized theory of collaborative caching
inferred← citeshttps://doi.org/10.1145/2318857.2254792openalex-snapshot
Providing fairness on shared-memory multiprocessors via process scheduling
inferred← citeshttps://doi.org/10.1145/2380403.2380435openalex-snapshot
Revisiting level-0 caches in embedded processors
inferred← citeshttps://doi.org/10.1145/2426642.2259012openalex-snapshot
A generalized theory of collaborative caching
inferred← citeshttps://doi.org/10.1145/2451116.2451153openalex-snapshot
HOTL
inferred← citeshttps://doi.org/10.1145/2463209.2488786openalex-snapshot
LEQA
inferred← citeshttps://doi.org/10.1145/2490301.2451153openalex-snapshot
HOTL
inferred← citeshttps://doi.org/10.1145/2499368.2451153openalex-snapshot
HOTL
inferred← citeshttps://doi.org/10.1145/2632215openalex-snapshot
A Portable Optimization Engine for Accelerating Irregular Data-Traversal Applications on SIMD Architectures
inferred← citeshttps://doi.org/10.1145/2989081.2989090openalex-snapshot
Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes
inferred← citeshttps://doi.org/10.1145/3018743.3018759openalex-snapshot
Thread Data Sharing in Cache
inferred← citeshttps://doi.org/10.1145/3158120openalex-snapshot
Analytical modeling of cache behavior for affine programs
inferred← citeshttps://doi.org/10.1145/3192366.3192402openalex-snapshot
Locality analysis through static parallel sampling
inferred← citeshttps://doi.org/10.1145/3233182openalex-snapshot
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics
inferred← citeshttps://doi.org/10.1145/3289602.3293901openalex-snapshot
Stop Crying Over Your Cache Miss Rate
inferred← citeshttps://doi.org/10.1145/3290367openalex-snapshot
Fast and exact analysis for LRU caches
inferred← citeshttps://doi.org/10.1145/3296979.3192402openalex-snapshot
Locality analysis through static parallel sampling
inferred← citeshttps://doi.org/10.1145/3314221.3314606openalex-snapshot
A fast analytical model of fully associative caches
inferred← citeshttps://doi.org/10.1145/3316480.3325518openalex-snapshot
Scalable Performance Prediction of Codes with Memory Hierarchy and Pipelines
inferred← citeshttps://doi.org/10.1145/3319008.3319021openalex-snapshot
Is the Stack Distance Between Test Case and Method Correlated With Test Effectiveness?
inferred← citeshttps://doi.org/10.1145/3422575.3422806openalex-snapshot
PPT-SASMM: Scalable Analytical Shared Memory Model
inferred← citeshttps://doi.org/10.1145/3450264openalex-snapshot
Machine Learning–enabled Scalable Performance Prediction of Scientific Codes
inferred← citeshttps://doi.org/10.1145/3456727.3463766openalex-snapshot
To move or not to move?
inferred← citeshttps://doi.org/10.1145/3458817.3476221openalex-snapshot
Hybrid, scalable, trace-driven performance modeling of GPGPUs
inferred← citeshttps://doi.org/10.1145/3466823openalex-snapshot
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs
inferred← citeshttps://doi.org/10.1145/3484199openalex-snapshot
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer
inferred← citeshttps://doi.org/10.1145/3519939.3523714openalex-snapshot
Warping cache simulation of polyhedral programs
inferred← citeshttps://doi.org/10.1145/3595178openalex-snapshot
Cache Optimization and Performance Modeling of Batched, Small, and Rectangular Matrix Multiplication on Intel, AMD, and Fujitsu Processors
inferred← citeshttps://doi.org/10.1145/3631882.3631885openalex-snapshot
LLVM Static Analysis for Program Characterization and Memory Reuse Profile Estimation
inferred← citeshttps://doi.org/10.1145/3656012openalex-snapshot
TAO: Re-Thinking DL-based Microarchitecture Simulation
inferred← citeshttps://doi.org/10.1145/780822.781140openalex-snapshot
A comparison of empirical and model-driven optimization
inferred← citeshttps://doi.org/10.1145/781131.781140openalex-snapshot
A comparison of empirical and model-driven optimization
inferred← citeshttps://doi.org/10.1145/996566.996652openalex-snapshot
High level cache simulation for heterogeneous multiprocessors
inferred← citeshttps://doi.org/10.1201/9781420043839.ch15openalex-snapshot
Computations on Iteration Spaces
inferred← citeshttps://doi.org/10.1609/icwsm.v8i1.14514openalex-snapshot
Of Pins and Tweets: Investigating How Users Behave Across Image- and Text-Based Social Networks
inferred← citeshttps://doi.org/10.23919/date.2017.7926958openalex-snapshot
AFEC: An analytical framework for evaluating cache performance in out-of-order processors
inferred← citeshttps://doi.org/10.3390/electronics7090172openalex-snapshot
Access Adaptive and Thread-Aware Cache Partitioning in Multicore Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1511.05585openalex-snapshot
Model-Driven Automatic Tiling with Cache Associativity Lattices
inferred← citeshttps://doi.org/10.48550/arxiv.1907.12666openalex-snapshot
Modeling Shared Cache Performance of OpenMP Programs using Reuse Distance
inferred← citeshttps://doi.org/10.5220/0004982405090516openalex-snapshot
Signature-based High-level Simulation of Microthreaded Many-core Architectures
inferred← citeshttps://doi.org/10.5555/2750482.2750490openalex-snapshot
Efficient MRC construction with SHARDS
inferred← citeshttps://doi.org/10.5626/jcse.2009.3.4.195openalex-snapshot
Bounding Worst-Case Data Cache Performance by Using Stack Distance
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