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Region-based compilation: Introduction, motivation, and initial experience

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-57877-3_28openalex-snapshot
Instruction scheduling over regions: A framework for scheduling across basic blocks
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1007/bf01205184openalex-snapshot
Compiling for the Cydra
inferredcites →https://doi.org/10.1007/bf01205185openalex-snapshot
The superblock: An effective technique for VLIW and superscalar compilation
inferredcites →https://doi.org/10.1007/bf03356742openalex-snapshot
Iterative Modulo Scheduling
inferredcites →https://doi.org/10.1007/bf03356743openalex-snapshot
Parallelization of Control Recurrences for ILP Processors
inferredcites →https://doi.org/10.1016/0141-1195(83)90118-3openalex-snapshot
Software engineering: A practitioner's approach
inferredcites →https://doi.org/10.1109/32.121752openalex-snapshot
Subprogram inlining: a study of its effects on program execution time
inferredcites →https://doi.org/10.1109/32.54294openalex-snapshot
Region scheduling: an approach for detecting and redistributing parallelism
inferredcites →https://doi.org/10.1109/hicss.1992.183141openalex-snapshot
Scalar program performance on multiple-instruction-issue processors with a limited number of registers
inferredcites →https://doi.org/10.1109/micro.1988.639244openalex-snapshot
Trace Selection For Compiling Large C Application Programs To Microcode
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1993.282760openalex-snapshot
Superblock formation using static program analysis
inferredcites →https://doi.org/10.1109/micro.1995.476813openalex-snapshot
Critical path reduction for scalar programs
inferredcites →https://doi.org/10.1109/micro.1995.476842openalex-snapshot
Unrolling-based optimizations for modulo scheduling
inferredcites →https://doi.org/10.1109/micro.1996.566456openalex-snapshot
Modulo scheduling of loops in control-intensive non-numeric programs
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/155090.155119openalex-snapshot
Branch prediction for free
inferredcites →https://doi.org/10.1145/173262.155119openalex-snapshot
Branch prediction for free
inferredcites →https://doi.org/10.1145/192724.192729openalex-snapshot
Height reduction of control recurrences for ILP processors
inferredcites →https://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/255305.255317openalex-snapshot
A compilation technique for software pipelining of loops with conditional jumps
inferredcites →https://doi.org/10.1145/53990.54021openalex-snapshot
Optimal loop parallelization
inferredcites →https://doi.org/10.1145/74818.74840openalex-snapshot
Inline function expansion for compiling C programs
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/88616.88621openalex-snapshot
The priority-based coloring approach to register allocation
inferredcites →https://doi.org/10.1145/960116.54014openalex-snapshot
Compiling C for vectorization, parallelization, and inline expansion
inferredcites →https://doi.org/10.1145/960116.54021openalex-snapshot
Optimal loop parallelization
inferredcites →https://doi.org/10.1145/960116.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.5555/110382.110438openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.5555/225160.225209openalex-snapshot
Unrolling-based optimizations for modulo scheduling
inferredcites →https://doi.org/10.5555/243846.243879openalex-snapshot
Modulo scheduling of loops in control-intensive non-numeric programs
inferredcites →https://doi.org/10.5555/62504.62511openalex-snapshot
Trace selection for compiling large C application programs to microcode

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-02063-6_11openalex-snapshot
Application-Aware Reliability and Security: The Trusted Illiac Experience
inferred← citeshttps://doi.org/10.1007/s11241-007-9030-5openalex-snapshot
A time-predictable VLIW processor and its compiler support
inferred← citeshttps://doi.org/10.1109/2.642817openalex-snapshot
Compilers for instruction-level parallelism
inferred← citeshttps://doi.org/10.1109/5.964445openalex-snapshot
Compiling for EPIC architectures
inferred← citeshttps://doi.org/10.1109/intera.2003.1192358openalex-snapshot
A region-based compilation infrastructure
inferred← citeshttps://doi.org/10.1109/pact.2000.888257openalex-snapshot
Region formation analysis with demand-driven inlining for region-based optimization
inferred← citeshttps://doi.org/10.1145/1457255.1457257openalex-snapshot
On the exploitation of loop-level parallelism in embedded applications
inferred← citeshttps://doi.org/10.1145/508791.508976openalex-snapshot
Evaluating the use of profiling by a region-based register allocator
inferred← citeshttps://doi.org/10.1145/782814.782836openalex-snapshot
Estimating cache misses and locality using stack distances
inferred← citeshttps://doi.org/10.1201/9781420040579.ch13openalex-snapshot
Register Allocation
inferred← citeshttps://doi.org/10.48550/arxiv.cs/0604043openalex-snapshot
Demand-driven Inlining in a Region-based Optimizer for ILP Architectures
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