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LCF_LSM, A system for specifying and verifying hardware

https://doi.org/10.48456/tr-41
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Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Executing temporal logic programs
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Recording and checking HOL proofs
inferred← citeshttps://doi.org/10.1007/978-1-4471-3544-9_14openalex-snapshot
Use of the OTTER theorem prover for the formal verification of hardware
inferred← citeshttps://doi.org/10.1007/978-1-4471-5260-6_2openalex-snapshot
Background
inferred← citeshttps://doi.org/10.1007/978-1-4613-2007-4_4openalex-snapshot
Formal Verification and Implementation of a Microprocessor
inferred← citeshttps://doi.org/10.1007/978-1-4615-3556-0_2openalex-snapshot
Formal Hardware Verification Methods: A Survey
inferred← citeshttps://doi.org/10.1007/978-3-642-84304-4_9openalex-snapshot
A Concept of Defining Semantics of Concurrent Microprograms
inferred← citeshttps://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
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Gordon's computer: A hardware verification case study in OBJ3
inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot
Algebraic Models of Correctness for Microprocessors
inferred← citeshttps://doi.org/10.1007/s002360050051openalex-snapshot
Algebraic models of microprocessors architecture and organisation
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Formal hardware specification and verification using prolog
inferred← citeshttps://doi.org/10.1016/0165-6074(89)90119-1openalex-snapshot
Verification oriented approach to concurrent microprogramming with the language C-MIDDLE
inferred← citeshttps://doi.org/10.1016/0165-6074(90)90277-gopenalex-snapshot
The OTTER environment for resolution-based proof of hardware correctness
inferred← citeshttps://doi.org/10.1016/0743-1066(87)90022-7openalex-snapshot
Logic programming and digital circuit analysis
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Validation of HOL Proofs by Proof Checking
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The use of machines to assist in rigorous proof
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ESTA: an expert system for DFT rule verification
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Programming a VIPER
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Striving toward correct FSMs: advances in design, formal verification, testing, and diagnosis
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A functional-based approach to formal VLSI design verification
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Formal verification of design correctness of sequential circuits based on theorem provers
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Resolution-based correctness proofs of synchronous circuits
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Michael John Caldwell Gordon (FRS 1994), 28 February 1948 -- 22 August 2017
inferred← citeshttps://doi.org/10.48456/tr-201openalex-snapshot
Formalizing abstraction mechanisms for hardware verification in higher order logic
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An algebraic framework for modelling and verifying microprocessors using HOL
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Experiences in Prolog-based DFT rule checking
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Resolution-based correctness proofs of synchronous circuits
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