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Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11758549_89openalex-snapshot
A Conservative Approach to SystemC Parallelization
inferredcites →https://doi.org/10.1007/978-3-642-04284-3_14openalex-snapshot
Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling
inferredcites →https://doi.org/10.1049/ic.2010.0141openalex-snapshot
A dynamic load balancing method for parallel simulation of accuracy adaptive TLMs
inferredcites →https://doi.org/10.1109/date.2011.5763309openalex-snapshot
jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip
inferredcites →https://doi.org/10.1109/ispa.2008.124openalex-snapshot
Relaxing Synchronization in a Parallel SystemC Kernel
inferredcites →https://doi.org/10.1109/memcod.2011.5970524openalex-snapshot
Modeling of time in discrete-event simulation of systems-on-chip
inferredcites →https://doi.org/10.1109/pads.2009.25openalex-snapshot
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
inferredcites →https://doi.org/10.1109/sies.2008.4577715openalex-snapshot
Scalably distributed SystemC simulation for embedded applications
inferredcites →https://doi.org/10.1145/1754405.1754406openalex-snapshot
Race analysis for systemc using model checking
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10766-013-0303-4openalex-snapshot
A Transaction-Based Environment for System Modeling and Parallel Simulation
inferred← citeshttps://doi.org/10.1007/s10766-020-00668-wopenalex-snapshot
Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation
inferred← citeshttps://doi.org/10.1016/j.vlsi.2020.12.006openalex-snapshot
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support
inferred← citeshttps://doi.org/10.1080/02533839.2016.1220840openalex-snapshot
Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045492openalex-snapshot
Event Delivery using Prediction for Faster Parallel SystemC Simulation
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045568openalex-snapshot
Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models
inferred← citeshttps://doi.org/10.1109/fdl53530.2021.9568385openalex-snapshot
Improving Parallelism in System Level Models by Assessing PDES Performance
inferred← citeshttps://doi.org/10.1109/hldvt.2016.7748262openalex-snapshot
A segment-aware multi-core scheduler for system C PDES
inferred← citeshttps://doi.org/10.1109/issoc.2014.6972446openalex-snapshot
Parallel and distributed simulation of networked multi-core systems
inferred← citeshttps://doi.org/10.1109/rsp.2015.7416547openalex-snapshot
Challenges for the parallelization of loosely timed SystemC programs
inferred← citeshttps://doi.org/10.1109/samos.2015.7363702openalex-snapshot
Parallel SystemC simulation for ESL design using flexible time decoupling
inferred← citeshttps://doi.org/10.1109/tcad.2020.2977064openalex-snapshot
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions
inferred← citeshttps://doi.org/10.1145/2987374openalex-snapshot
Parallel SystemC Simulation for ESL Design
inferred← citeshttps://doi.org/10.1145/3358194openalex-snapshot
Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models
inferred← citeshttps://doi.org/10.1145/3607888openalex-snapshot
Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116512openalex-snapshot
Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES
inferred← citeshttps://doi.org/10.3390/electronics5020022openalex-snapshot
Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study
inferred← citeshttps://doi.org/10.3850/9783981537079_0114openalex-snapshot
SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments
inferred← citeshttps://doi.org/10.3850/9783981537079_0325openalex-snapshot
A New Parallel SystemC Kernel Leveraging Manycore Architectures
inferred← citeshttps://doi.org/10.70675/4e5bd8c4z7554z46b1zb8ccz0f2f675c2020openalex-snapshot
Exploration des approches de synchronisation directes pour la simulation unifiée et de haut niveau des systèmes continus/discrets
inferred← citeshttps://doi.org/10.70675/a1093f4bz890dz41fazadb3z2437edfaabb8openalex-snapshot
Contribution à l'amélioration des plateformes virtuelles SystemC/TLM : configuration, communication et parallélisme
inferred← citeshttps://doi.org/10.70675/e095c17czd8a1z468bz95f9z40f8140ea3eeopenalex-snapshot
Parallel Standard-Compliant SystemC Simulation of Loosely-Timed Transaction Level Models
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