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Evaluation of multithreaded processors and thread-switch policies

https://doi.org/10.1007/bfb0024207
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bfb0024207openalex-snapshot
Evaluation of multithreaded processors and thread-switch policies
inferredcites →https://doi.org/10.1109/40.216748openalex-snapshot
Sparcle: an evolutionary processor design for large-scale multiprocessors
inferredcites →https://doi.org/10.1109/40.296166openalex-snapshot
Predicting and precluding problems with memory latency
inferredcites →https://doi.org/10.1109/isca.1994.288161openalex-snapshot
Characterization of Alpha AXP performance using TP and SPEC workloads
inferredcites →https://doi.org/10.1145/106972.106985openalex-snapshot
The interaction of architecture and operating system design
inferredcites →https://doi.org/10.1145/115952.115978openalex-snapshot
Comparative evaluation of latency reducing and tolerating techniques
inferredcites →https://doi.org/10.1145/115952.115988openalex-snapshot
Strategies for achieving improved processor throughput
inferredcites →https://doi.org/10.1145/191995.192017openalex-snapshot
Characterization of alpha AXP performance using TP and SPEC workloads
inferredcites →https://doi.org/10.1145/195473.195524openalex-snapshot
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
inferredcites →https://doi.org/10.1145/195473.195576openalex-snapshot
Interleaving
inferredcites →https://doi.org/10.1145/216585.216588openalex-snapshot
Hitting the memory wall
inferredcites →https://doi.org/10.1145/223982.224449openalex-snapshot
Simultaneous multithreading
inferredcites →https://doi.org/10.1145/225830.224449openalex-snapshot
Simultaneous multithreading
inferredcites →https://doi.org/10.1145/232973.232994openalex-snapshot
Evaluation of multithreaded uniprocessors for commercial application environments
inferredcites →https://doi.org/10.1145/2591635.2667161openalex-snapshot
The Tera computer system
inferredcites →https://doi.org/10.1145/77726.255132openalex-snapshot
The Tera computer system

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1006/jpdc.2000.1692openalex-snapshot
Characterization and Parallelization of Decision-Tree Induction
inferred← citeshttps://doi.org/10.1109/hpca.2001.903266openalex-snapshot
An architectural evaluation of Java TPC-W
inferred← citeshttps://doi.org/10.1109/isscc.1998.672449openalex-snapshot
A commercial multithreaded RISC processor
inferred← citeshttps://doi.org/10.1109/micro.2004.8openalex-snapshot
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
inferred← citeshttps://doi.org/10.1109/micro.2006.25openalex-snapshot
Fairness and Throughput in Switch on Event Multithreading
inferred← citeshttps://doi.org/10.1109/mm.2004.75openalex-snapshot
Helper threads via virtual multithreading
inferred← citeshttps://doi.org/10.1109/tc.2009.96openalex-snapshot
CSMT: Simultaneous Multithreading for Clustered VLIW Processors
inferred← citeshttps://doi.org/10.1145/1024393.1024411openalex-snapshot
Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform
inferred← citeshttps://doi.org/10.1145/1037187.1024411openalex-snapshot
Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform
inferred← citeshttps://doi.org/10.1145/1037947.1024411openalex-snapshot
Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform
inferred← citeshttps://doi.org/10.1145/1037949.1024411openalex-snapshot
Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform
inferred← citeshttps://doi.org/10.1145/1275937.1275939openalex-snapshot
Fairness enforcement in switch on event multithreading
inferred← citeshttps://doi.org/10.1145/1543753.1543755openalex-snapshot
Service level agreement for multithreaded processors
inferred← citeshttps://doi.org/10.1145/298151.298422openalex-snapshot
A dynamic scheduling logic for exploiting multiple functional units in single chip multithreaded architectures
inferred← citeshttps://doi.org/10.1147/rd.446.0885openalex-snapshot
A multithreaded PowerPC processor for commercial servers
inferred← citeshttps://doi.org/10.48550/arxiv.1603.09274openalex-snapshot
A Survey on Hardware and Software Support for Thread Level Parallelism
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95098openalex-snapshot
Improving multithreading performance for clustered VLIW architectures.
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