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Self-consistency checking

https://doi.org/10.1007/bfb0031806
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/978-1-4471-3558-6_12openalex-snapshot
Using Transformations and Verification in Circuit Design
inferredcites →https://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferredcites →https://doi.org/10.1007/bf01384073openalex-snapshot
Using transformations and verification in circuit design
inferredcites →https://doi.org/10.1109/12.368009openalex-snapshot
Formal modeling and verification of microprocessors
inferredcites →https://doi.org/10.1145/196244.196577openalex-snapshot
Automatic verification of pipelined microprocessors
inferredcites →https://doi.org/10.1145/240518.240623openalex-snapshot
Techniques for verifying superscalar microprocessors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-49519-3_21openalex-snapshot
Symbolic Simulation of the JEM1 Microprocessor
inferred← citeshttps://doi.org/10.1007/3-540-63875-x_40openalex-snapshot
Verification of pipelined microprocessors by comparing memory execution sequences in symbolic simulation
inferred← citeshttps://doi.org/10.1007/978-3-319-27340-2_75openalex-snapshot
Microprocessor Hazard Analysis Via Formal Verification of Parameterized Systems
inferred← citeshttps://doi.org/10.1007/978-3-319-63390-9_6openalex-snapshot
E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods
inferred← citeshttps://doi.org/10.1007/bfb0028737openalex-snapshot
Formal verification of out-of-order execution using incremental flushing
inferred← citeshttps://doi.org/10.1007/bfb0031821openalex-snapshot
Mechanically checking a lemma used in an automatic verification tool
inferred← citeshttps://doi.org/10.1007/s00165-012-0223-xopenalex-snapshot
Automatic verification of reduction techniques in Higher Order Logic
inferred← citeshttps://doi.org/10.1007/s10009-020-00591-yopenalex-snapshot
Utilizing parametric systems for detection of pipeline hazards
inferred← citeshttps://doi.org/10.1023/a:1014118529369openalex-snapshot
Formal Verification of Out-of-Order Execution with Incremental Flushing
inferred← citeshttps://doi.org/10.1109/aspdac.2010.5419811openalex-snapshot
A method for debugging of pipelined processors in formal verification by Correspondence Checking
inferred← citeshttps://doi.org/10.1109/csd.1998.657552openalex-snapshot
Verification of pipelined microprocessors by correspondence checking in symbolic ternary simulation
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218715openalex-snapshot
A-QED Verification of Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247903openalex-snapshot
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/dcfts.1999.814301openalex-snapshot
Invariant performance: a statement of task isolation useful for embedded application integration
inferred← citeshttps://doi.org/10.1109/mtv.2014.21openalex-snapshot
Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors
inferred← citeshttps://doi.org/10.1109/tcad.2004.829799openalex-snapshot
Self-Referential Verification for Gate-Level Implementations of Arithmetic Circuits
inferred← citeshttps://doi.org/10.1109/test.2015.7342397openalex-snapshot
A structured approach to post-silicon validation and debug using symbolic quick error detection
inferred← citeshttps://doi.org/10.1145/1531542.1531637openalex-snapshot
Enhancing bug hunting using high-level symbolic simulation
inferred← citeshttps://doi.org/10.1145/288548.289082openalex-snapshot
Formal verification of pipeline control using controlled token nets and abstract interpretation
inferred← citeshttps://doi.org/10.1145/513918.513998openalex-snapshot
Self-referential verification of gate-level implementations of arithmetic circuits
inferred← citeshttps://doi.org/10.34727/2020/isbn.978-3-85448-042-6_9openalex-snapshot
A Theoretical Framework for Symbolic Quick Error Detection
inferred← citeshttps://doi.org/10.34727/2021/isbn.978-3-85448-046-4_12openalex-snapshot
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition
inferred← citeshttps://doi.org/10.4204/eptcs.233.9openalex-snapshot
HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems
inferred← citeshttps://doi.org/10.6083/m4kh0kkxopenalex-snapshot
Structuring instruction-sets with higher-order functions
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