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Automatic generation of invariants in processor verification

https://doi.org/10.1007/bfb0031822
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-59293-8_237openalex-snapshot
STeP: The Stanford Temporal Prover
inferredcites →https://doi.org/10.1007/3-540-61474-5_80openalex-snapshot
Powerful techniques for the automatic generation of invariants
inferredcites →https://doi.org/10.1007/978-1-4471-3558-6_12openalex-snapshot
Using Transformations and Verification in Circuit Design
inferredcites →https://doi.org/10.1007/978-1-4612-4222-2openalex-snapshot
Temporal Verification of Reactive Systems
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot
Microprocessor design verification
inferredcites →https://doi.org/10.1007/bf01384073openalex-snapshot
Using transformations and verification in circuit design
inferredcites →https://doi.org/10.1007/bfb0031808openalex-snapshot
Validity checking for combinations of theories with equality
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1098/rsta.1992.0030openalex-snapshot
Occam in the specification and verification of microprocessors
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1145/357073.357079openalex-snapshot
Simplification by Cooperating Decision Procedures
inferredcites →https://doi.org/10.11575/prism/30386openalex-snapshot
PROVING A COMPUTER CORRECT IN HIGHER ORDER LOGIC
inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot
Efficient validity checking for processor verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_25openalex-snapshot
Formally Verifying Data and Control with Weak Reachability Invariants
inferred← citeshttps://doi.org/10.1007/3-540-63010-4_3openalex-snapshot
Deductive verification of real-time systems using STeP
inferred← citeshttps://doi.org/10.1007/3-540-64358-3_47openalex-snapshot
Deductive verification of hybrid systems using step
inferred← citeshttps://doi.org/10.1007/978-3-540-39724-3_15openalex-snapshot
Semi-formal Verification of Memory Systems by Symbolic Simulation
inferred← citeshttps://doi.org/10.1007/978-3-540-39910-0_4openalex-snapshot
Abstraction as the Key for Invariant Verification
inferred← citeshttps://doi.org/10.1007/978-3-540-45069-6_38openalex-snapshot
Strengthening Invariants by Symbolic Consistency Testing
inferred← citeshttps://doi.org/10.1007/978-3-642-20398-5_15openalex-snapshot
Instantiation-Based Invariant Discovery
inferred← citeshttps://doi.org/10.1007/bfb0028755openalex-snapshot
Computing abstractions of infinite state systems compositionally and automatically
inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot
Algebraic Models of Correctness for Microprocessors
inferred← citeshttps://doi.org/10.1016/s0304-3975(00)00088-8openalex-snapshot
Deductive verification of real-time systems using STeP
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1023/a:1024716316140openalex-snapshot
Formal Verification of a Complex Pipelined Processor
inferred← citeshttps://doi.org/10.1109/fmcad.2006.2openalex-snapshot
A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification
inferred← citeshttps://doi.org/10.1109/hldvt.2001.972816openalex-snapshot
Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core
inferred← citeshttps://doi.org/10.1109/iscas.1999.777794openalex-snapshot
Synthesis of checker EFSMs from timing diagram specifications
inferred← citeshttps://doi.org/10.1109/memcod.2003.1210090openalex-snapshot
Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions
inferred← citeshttps://doi.org/10.1109/mtv.2007.13openalex-snapshot
A Scalable Symbolic Simulator for Verilog RTL
inferred← citeshttps://doi.org/10.1145/288195.288218openalex-snapshot
Automatic generation of state invariants from requirements specifications
inferred← citeshttps://doi.org/10.1145/298595.298603openalex-snapshot
Checking properties of safety critical specifications using efficient decision procedures
inferred← citeshttps://doi.org/10.1145/3729331openalex-snapshot
Making Concurrent Hardware Verification Sequential
inferred← citeshttps://doi.org/10.29007/prxpopenalex-snapshot
Invariants and Robustness of BIP Models
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