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The Chip Is the Network: Toward a Science of Network-on-Chip Design
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/047120644xopenalex-snapshot
Self‐Similar Network Traffic and Performance Evaluation
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A Comprehensive Analytical Model for Wormhole Routing in Multicomputer Systems
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Branch-and-Bound Applications in Combinatorial Data Analysis
inferredcites →https://doi.org/10.1007/3-540-48311-x_20openalex-snapshot
Performance Analysis of Wormhole Switching with Adaptive Routing in a Two-Dimensional Torus
inferredcites →https://doi.org/10.1007/978-1-349-03521-2openalex-snapshot
Graph Theory with Applications
inferredcites →https://doi.org/10.1007/978-1-4471-3267-7openalex-snapshot
Markov Chains and Stochastic Stability
inferredcites →https://doi.org/10.1007/978-1-4684-0233-9openalex-snapshot
The Picture Book of Quantum Mechanics
inferredcites →https://doi.org/10.1007/978-3-540-30205-6_54openalex-snapshot
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
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Hitting Time Analysis for Stochastic Communication
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How to Solve It: Modern Heuristics
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Queueing analysis: A foundation of performance evaluation
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1016/j.sysarc.2007.07.004openalex-snapshot
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
inferredcites →https://doi.org/10.1016/s0378-4754(99)00125-1openalex-snapshot
Performance of data networks with random links
inferredcites →https://doi.org/10.1016/s1388-3437(97)80058-3openalex-snapshot
An analytical model for wormhole routing with finite size input buffers
inferredcites →https://doi.org/10.1063/1.2740566openalex-snapshot
Nature-inspired interconnects for self-assembled large-scale network-on-chip designs
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Introduction to Operations Research
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The quadratic assignment problem: A survey and recent developments
inferredcites →https://doi.org/10.1093/acprof:oso/9780198515906.001.0001openalex-snapshot
Evolution of networks from biological nets to the Internet and WWW
inferredcites →https://doi.org/10.1103/physrevlett.84.2529openalex-snapshot
Highly Optimized Tolerance: Robustness and Design in Complex Systems
inferredcites →https://doi.org/10.1103/physrevlett.86.5632openalex-snapshot
Bose-Einstein Condensation in Complex Networks
inferredcites →https://doi.org/10.1103/revmodphys.74.47openalex-snapshot
Statistical mechanics of complex networks
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/43.945302openalex-snapshot
Theory of latency-insensitive design
inferredcites →https://doi.org/10.1109/54.914596openalex-snapshot
Intra-task voltage scheduling for low-energy hard real-time applications
inferredcites →https://doi.org/10.1109/71.277793openalex-snapshot
Performance analysis of mesh interconnection networks with deterministic routing
inferredcites →https://doi.org/10.1109/71.97897openalex-snapshot
Limits on interconnection network performance
inferredcites →https://doi.org/10.1109/asap.2003.1212833openalex-snapshot
Physical planning for on-chip multiprocessor networks and switch fabrics
inferredcites →https://doi.org/10.1109/async.2007.18openalex-snapshot
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
inferredcites →https://doi.org/10.1109/cdc.2006.377282openalex-snapshot
Growing Well-connected Graphs
inferredcites →https://doi.org/10.1109/dac.2006.229271openalex-snapshot
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems
inferredcites →https://doi.org/10.1109/date.2004.1268999openalex-snapshot
×pipesCompiler: a tool for instantiating application specific networks on chip
inferredcites →https://doi.org/10.1109/date.2005.11openalex-snapshot
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
inferredcites →https://doi.org/10.1109/date.2005.137openalex-snapshot
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
inferredcites →https://doi.org/10.1109/date.2005.40openalex-snapshot
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
inferredcites →https://doi.org/10.1109/date.2006.243842openalex-snapshot
GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links
inferredcites →https://doi.org/10.1109/date.2006.243952openalex-snapshot
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study
inferredcites →https://doi.org/10.1109/date.2006.244007openalex-snapshot
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
inferredcites →https://doi.org/10.1109/date.2006.244033openalex-snapshot
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness
inferredcites →https://doi.org/10.1109/date.2006.244034openalex-snapshot
A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/date.2006.244069openalex-snapshot
Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs
inferredcites →https://doi.org/10.1109/date.2007.364538openalex-snapshot
Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks
inferredcites →https://doi.org/10.1109/dftvs.2005.45openalex-snapshot
Methodologies and algorithms for testing switch-based NoC interconnects
inferredcites →https://doi.org/10.1109/dsd.2003.1231923openalex-snapshot
A two-step genetic algorithm for mapping task graphs to a network on chip architecture
inferredcites →https://doi.org/10.1109/dsn.2002.1028901openalex-snapshot
Impact of deep submicron technology on dependability of VLSI circuits
inferredcites →https://doi.org/10.1109/dsn.2002.1028924openalex-snapshot
Modeling the effect of technology trends on the soft error rate of combinational logic
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/hpca.2003.1183554openalex-snapshot
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
inferredcites →https://doi.org/10.1109/hpca.2008.4658639openalex-snapshot
CMP network-on-chip overlaid with multi-band RF-interconnect
inferredcites →https://doi.org/10.1109/iccad.2005.1560111openalex-snapshot
Compiler-directed voltage scaling on communication links for reducing power consumption
inferredcites →https://doi.org/10.1109/iccd.1997.628902openalex-snapshot
Power constrained design of multiprocessor interconnection networks
inferredcites →https://doi.org/10.1109/iccd.2003.1240887openalex-snapshot
Efficient synthesis of networks on chip
inferredcites →https://doi.org/10.1109/iccd.2004.1347958openalex-snapshot
Thermal-aware IP virtualization and placement for networks-on-chip architecture
inferredcites →https://doi.org/10.1109/iccd.2004.1347959openalex-snapshot
Many-to-many core-switch mapping in 2-D mesh NoC architectures
inferredcites →https://doi.org/10.1109/iccd.2006.4380812openalex-snapshot
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles
inferredcites →https://doi.org/10.1109/iccd.2006.4380846openalex-snapshot
Reliability Support for On-Chip Memories Using Networks-on-Chip
inferredcites →https://doi.org/10.1109/iccd.2006.4380859openalex-snapshot
Implementation and Evaluation of On-Chip Network Architectures
inferredcites →https://doi.org/10.1109/icpp.2005.59openalex-snapshot
Peak Power Control for a QoS Capable On-Chip Network
inferredcites →https://doi.org/10.1109/icvd.2003.1183166openalex-snapshot
Interfacing cores with on-chip packet-switched networks
inferredcites →https://doi.org/10.1109/icvd.2004.1261037openalex-snapshot
On-chip networks: a scalable, communication-centric embedded system design paradigm
inferredcites →https://doi.org/10.1109/icvd.2005.113openalex-snapshot
ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis
inferredcites →https://doi.org/10.1109/infcom.2000.832534openalex-snapshot
Heuristics for Internet map discovery
inferredcites →https://doi.org/10.1109/ipdps.2000.846062openalex-snapshot
Wavelengths requirement for permutation routing in all-optical multistage interconnection networks
inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot
Virtual-channel flow control
inferredcites →https://doi.org/10.1109/iscas.2007.378464openalex-snapshot
Fault Tolerance Analysis of NoC Architectures
inferredcites →https://doi.org/10.1109/isqed.2007.169openalex-snapshot
Virtual Channels Planning for Networks-on-Chip
inferredcites →https://doi.org/10.1109/isscc.2004.1332639openalex-snapshot
A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform
inferredcites →https://doi.org/10.1109/isscc.2005.1493930openalex-snapshot
The design and implementation of a first-generation CELL processor
inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
inferredcites →https://doi.org/10.1109/issoc.2003.1267722openalex-snapshot
Highly scalable network on chip for reconfigurable systems
inferredcites →https://doi.org/10.1109/mascots.2006.9openalex-snapshot
A Statistical Traffic Model for On-Chip Interconnection Networks
inferredcites →https://doi.org/10.1109/mdt.2005.104openalex-snapshot
Analysis of error recovery schemes for networks on chips
inferredcites →https://doi.org/10.1109/mdt.2008.138openalex-snapshot
COSI: A Framework for the Design of Interconnection Networks
inferredcites →https://doi.org/10.1109/micro.2004.35openalex-snapshot
Thermal Modeling, Characterization and Management of On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2006.50openalex-snapshot
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/newcas.2005.1496682openalex-snapshot
Adaptive Scheduling for CDMA-Based-Networks-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2007.1openalex-snapshot
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
inferredcites →https://doi.org/10.1109/nocs.2007.40openalex-snapshot
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
inferredcites →https://doi.org/10.1109/nocs.2008.4492732openalex-snapshot
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
inferredcites →https://doi.org/10.1109/nocs.2008.4492736openalex-snapshot
Statistical Approach to NoC Design
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tc.2008.58openalex-snapshot
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
inferredcites →https://doi.org/10.1109/tc.2008.86openalex-snapshot
SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/tcad.2005.847907openalex-snapshot
Error control schemes for on-chip communication links: the energy-reliability tradeoff
inferredcites →https://doi.org/10.1109/tcad.2006.882474openalex-snapshot
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
inferredcites →https://doi.org/10.1109/tcad.2008.2003301openalex-snapshot
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
inferredcites →https://doi.org/10.1109/test.2005.1584020openalex-snapshot
A scalable test strategy for network-on-chip routers
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1109/tvlsi.2003.817546openalex-snapshot
Fixed-outline floorplanning: enabling hierarchical design
inferredcites →https://doi.org/10.1109/tvlsi.2003.820523openalex-snapshot
On-chip traffic modeling and synthesis for MPEG-2 video applications
inferredcites →https://doi.org/10.1109/tvlsi.2004.830919openalex-snapshot
An architecture and compiler for scalable on-chip communication
inferredcites →https://doi.org/10.1109/tvlsi.2006.871762openalex-snapshot
Linear-programming-based techniques for synthesis of network-on-chip architectures
inferredcites →https://doi.org/10.1109/tvlsi.2006.874359openalex-snapshot
Energy-efficient soft error-tolerant digital signal processing
inferredcites →https://doi.org/10.1109/tvlsi.2006.878263openalex-snapshot
"It's a small world after all": NoC performance optimization via long-range link insertion
inferredcites →https://doi.org/10.1111/j.2517-6161.1951.tb00080.xopenalex-snapshot
Some Problems in the Theory of Queues
inferredcites →https://doi.org/10.1126/science.220.4598.671openalex-snapshot
Optimization by Simulated Annealing
inferredcites →https://doi.org/10.1145/1016720.1016763openalex-snapshot
Power-aware communication optimization for networks-on-chips with voltage scalable links
inferredcites →https://doi.org/10.1145/1016720.1016765openalex-snapshot
Multi-objective mapping for mesh-based NoC architectures
inferredcites →https://doi.org/10.1145/1023833.1023849openalex-snapshot
High-level power analysis for on-chip networks
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.1145/1065579.1065648openalex-snapshot
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
inferredcites →https://doi.org/10.1145/1077603.1077695openalex-snapshot
A technique for low energy mapping and routing in network-on-chip architectures
inferredcites →https://doi.org/10.1145/1080695.1070004openalex-snapshot
Interconnections in Multi-Core Architectures
inferredcites →https://doi.org/10.1145/1080695.1070006openalex-snapshot
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
inferredcites →https://doi.org/10.1145/1081081.1081138openalex-snapshot
Fault tolerance overhead in network-on-chip flow control schemes
inferredcites →https://doi.org/10.1145/1084834.1084856openalex-snapshot
Key research problems in NoC design
inferredcites →https://doi.org/10.1145/1119772.1119817openalex-snapshot
Towards on-chip fault-tolerant communication
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1132952.1132953openalex-snapshot
A survey of research and practices of Network-on-chip
inferredcites →https://doi.org/10.1145/1176254.1176289openalex-snapshot
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1233501.1233573openalex-snapshot
Designing application-specific networks on chips with floorplan information
inferredcites →https://doi.org/10.1145/1255456.1255460openalex-snapshot
On-chip communication architecture exploration
inferredcites →https://doi.org/10.1145/1278480.1278509openalex-snapshot
Voltage-frequency island partitioning for GALS-based networks-on-chip
inferredcites →https://doi.org/10.1145/1278480.1278513openalex-snapshot
The case for low-power photonic networks on chip
inferredcites →https://doi.org/10.1145/1278480.1278546openalex-snapshot
Quantum-like effects in network-on-chip buffers behavior
inferredcites →https://doi.org/10.1145/1278480.1278650openalex-snapshot
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
inferredcites →https://doi.org/10.1145/1289816.1289845openalex-snapshot
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
inferredcites →https://doi.org/10.1145/1289816.1289846openalex-snapshot
Three-dimensional multiprocessor system-on-chip thermal optimization
inferredcites →https://doi.org/10.1145/1297666.1297677openalex-snapshot
Analysis and optimization of prediction-based flow control in networks-on-chip
inferredcites →https://doi.org/10.1145/1366110.1366193openalex-snapshot
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
inferredcites →https://doi.org/10.1145/1403375.1403676openalex-snapshot
Minimizing virtual channel buffer for routers in on-chip communication architectures
inferredcites →https://doi.org/10.1145/316188.316229openalex-snapshot
On power-law relationships of the Internet topology
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/378239.378557openalex-snapshot
An approach to incremental design of distributed embedded systems
inferredcites →https://doi.org/10.1145/383082.383092openalex-snapshot
Hard real-time scheduling for low-energy using stochastic data and DVS processors
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.1145/871506.871620openalex-snapshot
Energy optimization techniques in cluster interconnects
inferredcites →https://doi.org/10.1145/944645.944648openalex-snapshot
A modular simulation framework for architectural exploration of on-chip interconnection networks
inferredcites →https://doi.org/10.1145/951710.951721openalex-snapshot
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
inferredcites →https://doi.org/10.1155/2007/37627openalex-snapshot
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees
inferredcites →https://doi.org/10.1155/2007/68432openalex-snapshot
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic
inferredcites →https://doi.org/10.1155/2007/95348openalex-snapshot
Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip
inferredcites →https://doi.org/10.1166/jolpe.2007.138openalex-snapshot
Low Power and Energy Efficient Asynchronous Design
inferredcites →https://doi.org/10.1515/9781400841356openalex-snapshot
The Structure and Dynamics of Networks
inferredcites →https://doi.org/10.1561/1300000002openalex-snapshot
Scaling Laws for Ad Hoc Wireless Networks: An Information Theoretic Approach
inferredcites →https://doi.org/10.2307/253980openalex-snapshot
Theory of Linear and Integer Programming
inferredcites →https://doi.org/10.2307/2583863openalex-snapshot
Network Flows: Theory, Algorithms, and Applications.
inferredcites →https://doi.org/10.2307/2669582openalex-snapshot
Queueing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications
inferredcites →https://doi.org/10.2307/3611503openalex-snapshot
Foundations of the Theory of Probability
inferredcites →https://doi.org/10.3929/ethz-a-004284029openalex-snapshot
SPEA2: Improving the strength pareto evolutionary algorithm
inferredcites →https://doi.org/10.4218/etrij.06.0105.0254openalex-snapshot
Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks
inferredcites →https://doi.org/10.5555/1025127.1026011openalex-snapshot
Partitioning of Code for a Massively Parallel Machine
inferredcites →https://doi.org/10.5555/1266366.1266444openalex-snapshot
Toward a scalable test methodology for 2D-mesh Network-on-Chips
inferredcites →https://doi.org/10.5555/1266366.1266571openalex-snapshot
Congestion-controlled best-effort communication for networks-on-chip
inferredcites →https://doi.org/10.5555/1266366.1266601openalex-snapshot
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
inferredcites →https://doi.org/10.5555/1266366.1266602openalex-snapshot
Analytical router modeling for networks-on-chip performance analysis
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Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
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Micro-Network for SoC: Implementation of a 32-Port SPIN network
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Managing power consumption in networks on chips
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
inferredcites →https://doi.org/10.5860/choice.37-5722openalex-snapshot
Small worlds: the dynamics of networks between order and randomness
inferredcites →https://doi.org/10.5860/choice.40-1593openalex-snapshot
Handbook of applied optimization
inferredcites →https://doi.org/10.7551/mitpress/1425.003.0025openalex-snapshot
Performance Analysis of k-ary n-cube Interconnection Networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Network-on-Chip Routing Algorithms by Breaking Cycles
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An energy-aware online task mapping algorithm in NoC-based system
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A survey on energy-efficient methodologies and architectures of network-on-chip
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An efficient network on-chip architecture based on isolating local and non-local communications
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Bimodal packet aware scheduling for an OFDMA based on-chip RF interconnect
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System design of full HD MVC decoding on mesh-based multicore NoCs
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MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture
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Problems and challenges of emerging technology networks−on−chip: A review
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Performance evaluation and design tradeoffs of on-chip interconnect architectures
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Research directions in energy-sustainable cyber–physical systems
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A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
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Design of robust networks via reinforcement learning prompts the emergence of multi-backbones
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Online fault detection for Networks-on-Chip interconnect
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Workload Modeling and its Implications on Data-Center-on-a-Chip Optimization: From Mathematical Models to Control Algorithms
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An Analytical Channel Model for Emerging Wireless Networks-on-Chip
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An Effective Technique to Reduce Querying Routing Table for Mesh-based Network-on-Chip
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Disease diagnosis-on-a-chip: Large scale networks-on-chip based multicore platform for protein folding analysis
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A Traffic Model for Concurrent Core Tasks in Networks-on-Chip
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Exploring congestion phase transitions in vehicular traffic via topology and driver behavior modeling
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Using Transmission Lines for Global On-Chip Communication
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Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems—Overview, Challenges, and Opportunities
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An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads
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Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors
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Plasticity-on-Chip Design: Exploiting Self-Similarity for Data Communications
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Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
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Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale in Future Multiprocessor Platforms
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Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network
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A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems
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Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock
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The Problem of a Symmetric Graph with a Maximum Number of Vertices and Minimum Diameter
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RQRT: REDUCE QUERYING ROUTING TABLE FOR MESH-BASED NETWORK-ON-CHIP
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A New Simulator Based on Multi Core Processor with Improved Sense Amplifier
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Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip using Intel Sing-Chip Cloud Computer
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A structural analysis of evolved complex networks-on-chip
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Dynamic power management for multidomain system-on-chip platforms
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Mathematical Modeling and Control of Multifractal Workloads for Data-Center-on-a-Chip Optimization
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NoC Architectures as Enablers of Biological Discovery for Personalized and Precision Medicine
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A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures
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A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing
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Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels
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Performance Evaluation of NoC-Based Multicore Systems
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Optimization Models for Three On-Chip Network Problems
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A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles
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Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip
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Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip
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A general communication performance evaluation model based on routing path decomposition
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Design of robust networks via reinforcement learning prompt the emergence of multilayer backbones
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Características e especificidades da Metodologia de Análise de Redes Sociais
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VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip
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A design space exploration of transmission-line links for on-chip interconnect
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Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
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An efficient network on-chip architecture based on isolating local and non-local communications
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A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms
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NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions
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MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip
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