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A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/0-306-48727-6_4openalex-snapshot
Guaranteeing the Quality of Services in Networks on Chip
inferredcites →https://doi.org/10.1007/1-4020-3454-7_1openalex-snapshot
Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_12openalex-snapshot
xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/date.2004.1268854openalex-snapshot
Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
inferredcites →https://doi.org/10.1109/date.2004.1268972openalex-snapshot
Cost-performance trade-offs in networks on chip: a simulation-based approach
inferredcites →https://doi.org/10.1109/date.2004.1268998openalex-snapshot
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
inferredcites →https://doi.org/10.1109/iccd.2003.1240887openalex-snapshot
Efficient synthesis of networks on chip
inferredcites →https://doi.org/10.1109/icecs.2004.1399722openalex-snapshot
Automatic hardware-efficient SoC integration by QoS network on chip
inferredcites →https://doi.org/10.1109/icvd.2004.1261011openalex-snapshot
NoCGEN:a template based reuse methodology for Networks On Chip architecture
inferredcites →https://doi.org/10.1109/sac.2004.1322614openalex-snapshot
53.2 SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs
inferredcites →https://doi.org/10.1109/socc.2004.1362432openalex-snapshot
An asynchronous on-chip network router with quality-of-service (QoS) support
inferredcites →https://doi.org/10.1109/socc.2004.1362438openalex-snapshot
A virtual channel router for on-chip networks
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
inferredcites →https://doi.org/10.5555/968878.969037openalex-snapshot
Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
inferredcites →https://doi.org/10.5555/968879.969127openalex-snapshot
Cost-performance trade-offs in networks on chip: a simulation-based approach
inferredcites →https://doi.org/10.5555/968879.969205openalex-snapshot
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip
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Embedded Networks in Mobile Devices
inferred← citeshttps://doi.org/10.4233/uuid:2e8d335a-4251-41d9-b1fd-1697be9fbf2eopenalex-snapshot
Field Programmable Gate Arrays with Hardwired Networks on Chip
inferred← citeshttps://doi.org/10.46298/arima.1926openalex-snapshot
Ordonnancement de tâches hiérarchiques interdépendantes sous des exigences temporelles et objectif d’efficacité
inferred← citeshttps://doi.org/10.5121/ijdps.2012.3204openalex-snapshot
NOC: QOS Metrics Modelling And Analysis Based On Dynamic Routing
inferred← citeshttps://doi.org/10.5555/1129601.1129637openalex-snapshot
Application-specific network-on-chip architecture customization via long-range link insertion
inferred← citeshttps://doi.org/10.5555/1266366.1266393openalex-snapshot
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip
inferred← citeshttps://doi.org/10.5555/1266366.1266571openalex-snapshot
Congestion-controlled best-effort communication for networks-on-chip
inferred← citeshttps://doi.org/10.5555/1266366.1266572openalex-snapshot
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
inferred← citeshttps://doi.org/10.5555/1509633.1509701openalex-snapshot
Synthesis of networks on chips for 3D systems on chips
inferred← citeshttps://doi.org/10.5555/1870926.1871266openalex-snapshot
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
inferred← citeshttps://doi.org/10.5555/1874620.1874669openalex-snapshot
A high-level debug environment for communication-centric debug
inferred← citeshttps://doi.org/10.5555/3108905.3108914openalex-snapshot
Modeling and verification of network-on-chip using constrained-DEVS
inferred← citeshttps://doi.org/10.6100/ir639317openalex-snapshot
Monitoring-aware network-on-chip design
inferred← citeshttps://doi.org/10.6100/ir642808openalex-snapshot
Predictable embedded multiprocessor architecture for streaming applications
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