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Demystifying Complex Workload-DRAM Interactions
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.869367openalex-snapshot
SPEC CPU2000: measuring CPU performance in the New Millennium
inferredcites →https://doi.org/10.1109/cluster.2014.6968745openalex-snapshot
Evaluation of emerging memory technologies for HPC, data intensive applications
inferredcites →https://doi.org/10.1109/dsn.2015.57openalex-snapshot
Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field
inferredcites →https://doi.org/10.1109/dsn.2015.58openalex-snapshot
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
inferredcites →https://doi.org/10.1109/dsn.2016.30openalex-snapshot
PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM
inferredcites →https://doi.org/10.1109/dsn.2019.00017openalex-snapshot
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices
inferredcites →https://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/hpca.2006.1598122openalex-snapshot
Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
inferredcites →https://doi.org/10.1109/hpca.2012.6168944openalex-snapshot
Balancing DRAM locality and parallelism in shared memory CMP systems
inferredcites →https://doi.org/10.1109/hpca.2012.6168945openalex-snapshot
MORSE: Multi-objective reconfigurable self-optimizing memory scheduler
inferredcites →https://doi.org/10.1109/hpca.2014.6835946openalex-snapshot
Improving DRAM performance by parallelizing refreshes with accesses
inferredcites →https://doi.org/10.1109/hpca.2015.7056057openalex-snapshot
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
inferredcites →https://doi.org/10.1109/hpca.2016.7446093openalex-snapshot
Restore truncation for performance improvement in future DRAM systems
inferredcites →https://doi.org/10.1109/hpca.2016.7446095openalex-snapshot
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
inferredcites →https://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
inferredcites →https://doi.org/10.1109/hpca.2017.62openalex-snapshot
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
inferredcites →https://doi.org/10.1109/hpca.2018.00026openalex-snapshot
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
inferredcites →https://doi.org/10.1109/hpca.2019.00011openalex-snapshot
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
inferredcites →https://doi.org/10.1109/hpcc-css-icess.2015.166openalex-snapshot
SiNUCA: A Validated Micro-Architecture Simulator
inferredcites →https://doi.org/10.1109/iccd.2014.6974655openalex-snapshot
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost
inferredcites →https://doi.org/10.1109/iccd.2018.00051openalex-snapshot
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines
inferredcites →https://doi.org/10.1109/iceccs.2014.27openalex-snapshot
Behavior Gaps and Relations between Operating System and Applications on Accessing DRAM
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/iiswc.2012.6402918openalex-snapshot
A quantitative study of irregular programs on GPUs
inferredcites →https://doi.org/10.1109/imw.2013.6582088openalex-snapshot
Memory scaling: A systems architecture perspective
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/ispass.2013.6557153openalex-snapshot
Exascale workload characterization and architecture implications
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/micro.2004.22openalex-snapshot
Memory Controller Optimizations for Web Servers
inferredcites →https://doi.org/10.1109/micro.2006.44openalex-snapshot
Scalable Cache Miss Handling for High Memory-Level Parallelism
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2010.22openalex-snapshot
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2014.47openalex-snapshot
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
inferredcites →https://doi.org/10.1109/micro.2016.7783760openalex-snapshot
Improving bank-level parallelism for irregular applications
inferredcites →https://doi.org/10.1109/micro.2018.00032openalex-snapshot
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration
inferredcites →https://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferredcites →https://doi.org/10.1109/pact.2015.51openalex-snapshot
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM
inferredcites →https://doi.org/10.1109/tc.2004.1304814openalex-snapshot
IEEE Transactions on Computers
inferredcites →https://doi.org/10.1109/tpds.2016.2526003openalex-snapshot
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling
inferredcites →https://doi.org/10.1109/vlsit.2012.6242474openalex-snapshot
Hybrid memory cube new DRAM architecture increases density and performance
inferredcites →https://doi.org/10.1145/1133956.1133970openalex-snapshot
Decomposing memory performance
inferredcites →https://doi.org/10.1145/1400751.1400799openalex-snapshot
Distributed order scheduling and its application to multi-core dram controllers
inferredcites →https://doi.org/10.1145/1669112.1669119openalex-snapshot
Complexity effective memory access scheduling for many-core accelerator architectures
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1807128.1807152openalex-snapshot
Benchmarking cloud serving systems with YCSB
inferredcites →https://doi.org/10.1145/1998582.1998590openalex-snapshot
Memory power management via dynamic voltage/frequency scaling
inferredcites →https://doi.org/10.1145/2150976.2150989openalex-snapshot
Cosmic rays don't strike twice
inferredcites →https://doi.org/10.1145/2155620.2155663openalex-snapshot
Parallel application memory scheduling
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2228360.2228513openalex-snapshot
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
inferredcites →https://doi.org/10.1145/2591971.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/2694344.2694348openalex-snapshot
Memory Errors in Modern Systems
inferredcites →https://doi.org/10.1145/2896377.2901453openalex-snapshot
Understanding Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/2896377.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferredcites →https://doi.org/10.1145/3078505.3078533openalex-snapshot
Design-Induced Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/3078505.3078590openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferredcites →https://doi.org/10.1145/3123939.3123945openalex-snapshot
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
inferredcites →https://doi.org/10.1145/3219617.3219661openalex-snapshot
What Your DRAM Power Models Are Not Telling You
inferredcites →https://doi.org/10.1145/3240302.3240315openalex-snapshot
A performance & power comparison of modern high-speed DRAM architectures
inferredcites →https://doi.org/10.1145/3297663.3310311openalex-snapshot
Memory Centric Characterization and Analysis of SPEC CPU2017 Suite
inferredcites →https://doi.org/10.1145/360128.360134openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1147/rd.413.0265openalex-snapshot
Prefetching and memory system behavior of the SPEC95 benchmark suite
inferredcites →https://doi.org/10.1147/rd.462.0187openalex-snapshot
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
inferredcites →https://doi.org/10.1184/r1/6468908.v1openalex-snapshot
Improving DRAM Performance by Parallelizing Refreshes with Accesses
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems
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A Novel System Simulation Framework for HBM2 FPGA Platforms
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File Prefetching Accuracy Enhancement Using Deep Learning Approaches
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NDP-RANK: Prediction and ranking of NDP systems performance using machine learning
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PARL: Page Allocation in hybrid main memory using Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/access.2024.3514377openalex-snapshot
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
inferred← citeshttps://doi.org/10.1109/ccgrid59990.2024.00061openalex-snapshot
BlueJay: A Platform to Quantifying the Impact of Memory Latency on Datacenter Application Performance
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AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408437openalex-snapshot
Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408512openalex-snapshot
SAGe: A Lightweight Algorithm-Architecture Co-Design for Mitigating the Data Preparation Bottleneck in Large-Scale Genome Sequence Analysis
inferred← citeshttps://doi.org/10.1109/icde60146.2024.00300openalex-snapshot
Accelerating Aggregation Using a Real Processing-in-Memory System
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00054openalex-snapshot
MegIS: High-Performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00066openalex-snapshot
GRAINS: Enabling High-Performance and Low-Cost Graph-Based Genome Analysis via Storage-Aware Algorithm-Architecture Co-Design
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00118openalex-snapshot
DICE: Detailed Inter-Chiplet End-to-End Phy Modeling for Accurate Chiplet Simulation
inferred← citeshttps://doi.org/10.1109/islped65674.2025.11261765openalex-snapshot
Repurpose Accel-Sim for Next Generation NVIDIA Jetson GPU Architectural Design
inferred← citeshttps://doi.org/10.1109/tc.2025.3627945openalex-snapshot
TPDA-DRAM: A Variation-Aware DRAM Improving System Performance via In-Situ Timing Margin Detection and Adaptive Mitigation
inferred← citeshttps://doi.org/10.1109/tcad.2023.3238292openalex-snapshot
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration
inferred← citeshttps://doi.org/10.1109/tcsi.2022.3222573openalex-snapshot
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
inferred← citeshttps://doi.org/10.1109/tpds.2025.3553092openalex-snapshot
Accelerating Sparse Tensor Decomposition Using Adaptive Linearized Representation
inferred← citeshttps://doi.org/10.1109/vlsid64188.2025.00102openalex-snapshot
Efficient Mitigation of DRAM Row Buffer Conflict Using Request Clustering in Manycore Systems
inferred← citeshttps://doi.org/10.1145/3547658openalex-snapshot
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations
inferred← citeshttps://doi.org/10.1145/3566097.3567859openalex-snapshot
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture
inferred← citeshttps://doi.org/10.1145/3649455openalex-snapshot
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration
inferred← citeshttps://doi.org/10.1145/3695053.3731116openalex-snapshot
REIS: A High-Performance and Energy-Efficient Retrieval System with In-Storage Processing
inferred← citeshttps://doi.org/10.1145/3725843.3756081openalex-snapshot
RICH Prefetcher: Storing Rich Information in Memory to Trade Capacity and Bandwidth for Latency Hiding
inferred← citeshttps://doi.org/10.1145/3725843.3756106openalex-snapshot
Ghost Threading: Helper-Thread Prefetching for Real Systems
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539690openalex-snapshot
MemoryIslands: A Federated Approach for Efficient Memory Mappings
inferred← citeshttps://doi.org/10.3389/fnins.2022.937782openalex-snapshot
EnforceSNN: Enabling resilient and energy-efficient spiking neural network inference considering approximate DRAMs for embedded systems
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