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Managing GPU Concurrency in Heterogeneous Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.jpdc.2013.07.014openalex-snapshot
Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture
inferredcites →https://doi.org/10.1109/hotchips.2009.7478342openalex-snapshot
The OpenCL specification
inferredcites →https://doi.org/10.1109/hpca.2001.903256openalex-snapshot
Self-tuned congestion control for multiprocessor networks
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/hpca.2012.6168944openalex-snapshot
Balancing DRAM locality and parallelism in shared memory CMP systems
inferredcites →https://doi.org/10.1109/hpca.2012.6168947openalex-snapshot
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
inferredcites →https://doi.org/10.1109/hpca.2013.6522311openalex-snapshot
Application-to-core mapping policies to reduce memory system interference in multi-core systems
inferredcites →https://doi.org/10.1109/hpca.2014.6835945openalex-snapshot
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/iiswc.2012.6402918openalex-snapshot
A quantitative study of irregular programs on GPUs
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/micro.2010.39openalex-snapshot
Memory Latency Reduction via Thread Throttling
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2012.16openalex-snapshot
Cache-Conscious Wavefront Scheduling
inferredcites →https://doi.org/10.1109/mm.2008.31openalex-snapshot
NVIDIA Tesla: A Unified Graphics and Computing Architecture
inferredcites →https://doi.org/10.1109/pact.2013.6618806openalex-snapshot
Neither more nor less: optimizing thread-level parallelism for GPGPUs
inferredcites →https://doi.org/10.1109/sbac-pad.2012.44openalex-snapshot
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1736020.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1868447.1868459openalex-snapshot
Next generation on-chip networks
inferredcites →https://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferredcites →https://doi.org/10.1145/2155620.2155656openalex-snapshot
Improving GPU performance via large warps and two-level warp scheduling
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2228360.2228513openalex-snapshot
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
inferredcites →https://doi.org/10.1145/2342356.2342436openalex-snapshot
On-chip networks from a networking perspective
inferredcites →https://doi.org/10.1145/2463209.2488779openalex-snapshot
A heterogeneous multiple network-on-chip design
inferredcites →https://doi.org/10.1145/2485922.2485951openalex-snapshot
Orchestrated scheduling and prefetching for GPGPUs
inferredcites →https://doi.org/10.1145/2504906openalex-snapshot
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
inferredcites →https://doi.org/10.1145/2576779.2576780openalex-snapshot
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
inferredcites →https://doi.org/10.1145/2588768.2576780openalex-snapshot
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.5555/2523721.2523745openalex-snapshot
Neither more nor less: optimizing thread-level parallelism for GPGPUs
inferredcites →https://doi.org/10.7873/date2014.032openalex-snapshot
Energy-efficient scheduling for memory-intensive GPGPU workloads
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Journey of Embedded and Cyber-Physical Systems : Essays Dedicated to Peter Marwedel on the Occasion of His 70th Birthday
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Reflecting on Self-Aware Systems-on-Chip
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Towards Conflict-Aware Workload Co-execution on SX-Aurora TSUBASA
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General-Purpose Graphics Processor Architectures
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Machine Learning for Heterogeneous Manycore Design
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Cache Reuse Aware Replacement Policy for Improving GPU Cache Performance
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Godiva: green on-chip interconnection for DNNs
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Conflict-aware workload co-execution on SX-aurora TSUBASA
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A power-performance balanced network-on-chip for mixed CPU-GPU systems
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An effective scheme for memory congestion reduction in multi-core environment
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WITHDRAWN: An investigative analysis of RFiop: RF-memory path to address on-package I/O pad and memory controller scalability
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A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
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Optimizing Sorting Algorithms Using Ubiquitous Multi-core Massively Parallel GPGPU Processors
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Walter: Wide I/O Scaling of Number of Memory Controllers Versus Frequency and Voltage
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HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments
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GPU Parallel Optimization of Hyperspectral Image Kernel Sparse Representation Classification Based on Spatial-Spectral Graph Regularization
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Optimizing on-demand GPUs in the Cloud for Deep Learning Applications Training
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Advancing Design and Runtime Management of AI Applications with AI-SPRINT (Position Paper)
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Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU Applications
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446062openalex-snapshot
Warped-preexecution: A GPU pre-execution approach for improving latency hiding
inferred← citeshttps://doi.org/10.1109/hpca.2018.00030openalex-snapshot
Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management
inferred← citeshttps://doi.org/10.1109/hpca.2018.00048openalex-snapshot
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00059openalex-snapshot
Improving GPU Multi-tenancy with Page Walk Stealing
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00078openalex-snapshot
Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/iccd.2018.00050openalex-snapshot
Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture
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DIDO: Dynamic Pipelines for In-Memory Key-Value Stores on Coupled CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/icpads60453.2023.00264openalex-snapshot
DPBC-VCP: A Network-On-Chip Prioritization Mechanism Combined with VCP for CPU-GPU Heterogeneous Systems
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Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications
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Performance characterization, prediction, and optimization for heterogeneous systems with multi-level memory interference
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Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors
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Analyzing Deep Learning Model Inferences for Image Classification using OpenVINO
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The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs
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COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices
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Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach
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A Low-Cost Conflict-Free NoC Architecture for Heterogeneous Multicore Systems
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Neda: Supporting Direct Inter-Core Neighbor Data Exchange in GPUs
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Zorua: A holistic approach to resource virtualization in GPUs
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OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures
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Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
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Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
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Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM
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Analyzing and Leveraging Remote-Core Bandwidth for Enhanced Performance in GPUs
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TPE: XPU-Point: Simulator-Agnostic Sample Selection Methodology for Heterogeneous CPU-GPU Applications
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ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments
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Optimizing the heterogeneous network on-chip design in manycore architectures
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Hierarchical Scheduling in on-demand GPU-as-a-Service Systems
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HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures
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CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
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On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems
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Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems
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Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems
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MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
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BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling
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RTGPU: Real-Time GPU Scheduling of Hard Deadline Parallel Tasks With Fine-Grain Utilization
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ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures
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RAMON: Region-Aware Memory Controller
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Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability
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A Stall-Aware Warp Scheduling for Dynamically Optimizing Thread-level Parallelism in GPGPUs
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Anatomy of GPU Memory System for Multi-Application Execution
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Enabling coordinated register allocation and thread-level parallelism optimization for GPUs
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Exploiting Core Criticality for Enhanced GPU Performance
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Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture
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Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors
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Exploiting Core Criticality for Enhanced GPU Performance
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Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms
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Quality of Service Support for Fine-Grained Sharing on GPUs
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Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
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Understanding object-level memory access patterns across the spectrum
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Topology-aware GPU scheduling for learning workloads in cloud environments
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3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training
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Mitigating bitline crosstalk noise in DRAM memories
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Quality of Service Support for Fine-Grained Sharing on GPUs
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Hybrid on-chip communication architectures for heterogeneous manycore systems
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Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
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Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
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A Framework for Memory Oversubscription Management in Graphics Processing Units
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Opportunistic computing in GPU architectures
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Thread Batching for High-performance Energy-efficient GPU Memory Design
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A Unified Optimization Approach for CNN Model Inference on Integrated GPUs
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Efficient Nearest-Neighbor Data Sharing in GPUs
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ApproxNet: Content and Contention-Aware Video Object Classification System for Embedded Clients
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Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design
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Query Processing on Heterogeneous CPU/GPU Systems
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Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
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OASIS: Optimized Adaptive System for Intelligent SLAM
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Learning-Assisted Adaptive Hybrid Interconnection Design for Chiplet-Based Heterogeneous Systems
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Structure-Derived Bottleneck-Aware Scheduling for Multitasking MCM-GPUs
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The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
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The Main Memory System: Challenges and Opportunities
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Models and techniques for designing mobile system-on-chip devices
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Research Problems and Opportunities in Memory Systems
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Architectural and runtime enhancements for dynamically controlled multi-level concurrency on GPUs
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Improving the global memory efficiency in GPU-based systems
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Improving GPU performance through instruction redistribution and diversification
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General-Purpose Graphics Processor Architectures
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Throughput optimization and resource allocation on GPUs under multi-application execution
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Intelligent Architectures for Intelligent Computing Systems
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Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management
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Scaling Up Large-Scale Graph Processing for GPU-Accelerated Heterogeneous Systems
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ApproxNet: Content and Contention-Aware Video Analytics System for Embedded Clients
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Memory hierarchies for future HPC architectures
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Improving resource efficiency in virtualized datacenters
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