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Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Runahead execution: an alternative to very large instruction windows for out-of-order processors
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Proceedings. 11th International Symposium on High-Performance Computer Architecture
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Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/hpca.2009.4798280openalex-snapshot
Criticality-based optimizations for efficient load processing
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/hpca.2012.6168947openalex-snapshot
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
inferredcites →https://doi.org/10.1109/hpca.2013.6522311openalex-snapshot
Application-to-core mapping policies to reduce memory system interference in multi-core systems
inferredcites →https://doi.org/10.1109/hpca.2013.6522356openalex-snapshot
MISE: Providing performance predictability and improving fairness in shared main memory systems
inferredcites →https://doi.org/10.1109/iccd.2014.6974655openalex-snapshot
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/iiswc.2010.5650274openalex-snapshot
A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads
inferredcites →https://doi.org/10.1109/iiswc.2015.9openalex-snapshot
Characterization and Throttling-Based Mitigation of Memory Interference for Heterogeneous Smartphones
inferredcites →https://doi.org/10.1109/ipdpsw.2017.37openalex-snapshot
Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors
inferredcites →https://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/ispass.2006.1620807openalex-snapshot
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures
inferredcites →https://doi.org/10.1109/isscc.2011.5746311openalex-snapshot
A fully integrated multi-CPU, GPU and memory controller 32nm processor
inferredcites →https://doi.org/10.1109/l-ca.2011.32openalex-snapshot
DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/micro.2004.4openalex-snapshot
Adaptive History-Based Memory Schedulers
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2014.62openalex-snapshot
Managing GPU Concurrency in Heterogeneous Architectures
inferredcites →https://doi.org/10.1109/mm.2014.10openalex-snapshot
Haswell: The Fourth-Generation Intel Core Processor
inferredcites →https://doi.org/10.1109/mm.2014.3openalex-snapshot
Kabini: An AMD Accelerated Processing Unit System on A Chip
inferredcites →https://doi.org/10.1109/pact.2015.38openalex-snapshot
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
inferredcites →https://doi.org/10.1109/pact20333.2013openalex-snapshot
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1109/sc.2014.16openalex-snapshot
Managing DRAM Latency Divergence in Irregular GPGPU Applications
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/166117.166147openalex-snapshot
Hierarchical Z-buffer visibility
inferredcites →https://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1736020.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/2155620.2155663openalex-snapshot
Parallel application memory scheduling
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2228360.2228513openalex-snapshot
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
inferredcites →https://doi.org/10.1145/2485922.2485930openalex-snapshot
Improving memory scheduling via processor-side load criticality information
inferredcites →https://doi.org/10.1145/2485922.2485951openalex-snapshot
Orchestrated scheduling and prefetching for GPGPUs
inferredcites →https://doi.org/10.1145/2830772.2830803openalex-snapshot
The application slowdown model
inferredcites →https://doi.org/10.1145/2896377.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferredcites →https://doi.org/10.1145/2925426.2926266openalex-snapshot
Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors
inferredcites →https://doi.org/10.1145/3307650openalex-snapshot
Proceedings of the 46th International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1515/9781683922902openalex-snapshot
Introduction to 3D Game Programming with DirectX 12
inferredcites →https://doi.org/10.5555/2523721.2523745openalex-snapshot
Neither more nor less: optimizing thread-level parallelism for GPGPUs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.suscom.2024.101047openalex-snapshot
Nearest data processing in GPU
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247878openalex-snapshot
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)
inferred← citeshttps://doi.org/10.1109/indin.2018.8471962openalex-snapshot
Deadline-aware Memory Scheduler and Governor for Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/socc.2018.8618555openalex-snapshot
Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup
inferred← citeshttps://doi.org/10.1109/tc.2019.2943855openalex-snapshot
Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCs
inferred← citeshttps://doi.org/10.1109/twc.2021.3088910openalex-snapshot
Energy-Efficient Resource Management for Federated Edge Learning With CPU-GPU Heterogeneous Computing
inferred← citeshttps://doi.org/10.1145/3400286.3418230openalex-snapshot
A Cache Contention-aware Run-time Scheduling for Power-constrained Asymmetric Multicore Processors
inferred← citeshttps://doi.org/10.1631/fitee.2200449openalex-snapshot
A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system
inferred← citeshttps://doi.org/10.2139/ssrn.5373047openalex-snapshot
Efficient Design and Interface for Unified Dram Memory in Shared Cpu-Gpu Address Spaces
inferred← citeshttps://doi.org/10.48047/nq.2020.18.8.nq20238openalex-snapshot
Tile-based Multi-core Processor with Transactional Memory for Efficient Resource Utilization
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