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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/b978-0-122-66722-0.x5001-5openalex-snapshot
Machine Vision for Three-Dimensional Scenes
inferredcites →https://doi.org/10.1016/j.cviu.2007.09.014openalex-snapshot
Speeded-Up Robust Features (SURF)
inferredcites →https://doi.org/10.1049/iet-cdt.2012.0118openalex-snapshot
AMBA bus hardware accelerator IP for Viola–Jones face detection
inferredcites →https://doi.org/10.1109/cvpr.2001.990517openalex-snapshot
Rapid object detection using a boosted cascade of simple features
inferredcites →https://doi.org/10.1109/fpt.2003.1275774openalex-snapshot
Beyond performance: secure and fair memory management for multiple systems on a chip
inferredcites →https://doi.org/10.1109/gcce.2013.6664775openalex-snapshot
Hardware-accelerator design for energy-efficient acoustic feature extraction
inferredcites →https://doi.org/10.1109/gcce31049.2013openalex-snapshot
2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/hpca.2012.6168944openalex-snapshot
Balancing DRAM locality and parallelism in shared memory CMP systems
inferredcites →https://doi.org/10.1109/hpca.2013.6522311openalex-snapshot
Application-to-core mapping policies to reduce memory system interference in multi-core systems
inferredcites →https://doi.org/10.1109/hpca.2013.6522354openalex-snapshot
Tiered-latency DRAM: A low latency and low cost DRAM architecture
inferredcites →https://doi.org/10.1109/hpca.2013.6522356openalex-snapshot
MISE: Providing performance predictability and improving fairness in shared main memory systems
inferredcites →https://doi.org/10.1109/hpca.2014.6835946openalex-snapshot
Improving DRAM performance by parallelizing refreshes with accesses
inferredcites →https://doi.org/10.1109/hpca.2015.7056017openalex-snapshot
Exploring architectural heterogeneity in intelligent vision systems
inferredcites →https://doi.org/10.1109/hpca.2015.7056057openalex-snapshot
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
inferredcites →https://doi.org/10.1109/iccd.2009.5413123openalex-snapshot
Accelerating mobile augmented reality on a handheld platform
inferredcites →https://doi.org/10.1109/iccd.2014.6974655openalex-snapshot
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost
inferredcites →https://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/isca.2012.6237032openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1109/isca.2012.6237036openalex-snapshot
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
inferredcites →https://doi.org/10.1109/isscc.2012.6176984openalex-snapshot
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications
inferredcites →https://doi.org/10.1109/isscc.2015.7063059openalex-snapshot
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications
inferredcites →https://doi.org/10.1109/isvdat.2014.6881070openalex-snapshot
Hardware accelerator for real-time image resizing
inferredcites →https://doi.org/10.1109/l-ca.2011.1openalex-snapshot
Fairness Metrics for Multi-Threaded Processors
inferredcites →https://doi.org/10.1109/lca.2015.2414456openalex-snapshot
Ramulator: A Fast and Extensible DRAM Simulator
inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot
An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/micro.2004.28openalex-snapshot
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
inferredcites →https://doi.org/10.1109/micro.2004.4openalex-snapshot
Adaptive History-Based Memory Schedulers
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2010.39openalex-snapshot
Memory Latency Reduction via Thread Throttling
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2014.47openalex-snapshot
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
inferredcites →https://doi.org/10.1109/micro.2014.60openalex-snapshot
Short-Circuiting Memory Traffic in Handheld Platforms
inferredcites →https://doi.org/10.1109/micro.2014.62openalex-snapshot
Managing GPU Concurrency in Heterogeneous Architectures
inferredcites →https://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferredcites →https://doi.org/10.1109/rtas.2013.6531079openalex-snapshot
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms
inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot
Bounding memory interference delay in COTS-based multi-core systems
inferredcites →https://doi.org/10.1109/sbac-pad.2012.44openalex-snapshot
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks
inferredcites →https://doi.org/10.1109/secon.2013.6567367openalex-snapshot
Time-predictable DRAM access scheduling algorithms for real-time multicore processors
inferredcites →https://doi.org/10.1109/tcsvt.2005.846412openalex-snapshot
An efficient quality-aware memory controller for multimedia platform SoC
inferredcites →https://doi.org/10.1109/tcsvt.2011.2162760openalex-snapshot
High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction
inferredcites →https://doi.org/10.1109/vdat34131.2015openalex-snapshot
2015 19th International Symposium on VLSI Design and Test
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/1400751.1400799openalex-snapshot
Distributed order scheduling and its application to multi-core dram controllers
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1736020.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1868447.1868459openalex-snapshot
Next generation on-chip networks
inferredcites →https://doi.org/10.1145/2155620.2155663openalex-snapshot
Parallel application memory scheduling
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2228360.2228513openalex-snapshot
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
inferredcites →https://doi.org/10.1145/2342356.2342436openalex-snapshot
On-chip networks from a networking perspective
inferredcites →https://doi.org/10.1145/2366231.2337202openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1145/2370816.2370869openalex-snapshot
A software memory partition approach for eliminating bank-level interference in multicore systems
inferredcites →https://doi.org/10.1145/238721.238766openalex-snapshot
A hierarchial CPU scheduler for multimedia operating systems
inferredcites →https://doi.org/10.1145/2591971.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/2637364.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/268998.266677openalex-snapshot
The design, implementation and evaluation of SMART
inferredcites →https://doi.org/10.1145/2830772.2830803openalex-snapshot
The application slowdown model
inferredcites →https://doi.org/10.1145/319151.319169openalex-snapshot
Borrowed-virtual-time (BVT) scheduling
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.1184/r1/6468908.v1openalex-snapshot
Improving DRAM Performance by Parallelizing Refreshes with Accesses
inferredcites →https://doi.org/10.1184/r1/6469358openalex-snapshot
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
inferredcites →https://doi.org/10.1184/r1/6469403openalex-snapshot
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
inferredcites →https://doi.org/10.13140/rg.2.1.1912.4965openalex-snapshot
An Isotropic 3x3 Image Gradient Operator
inferredcites →https://doi.org/10.5555/1251229.1251233openalex-snapshot
Surplus fair scheduling: a proportional-share CPU scheduling algorithm for symmetric multiprocessors
inferredcites →https://doi.org/10.5555/1267638.1267639openalex-snapshot
Lottery scheduling: flexible proportional-share resource management
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-69035-3_17openalex-snapshot
A QoS-Aware Resource Allocation Controller for Function as a Service (FaaS) Platform
inferred← citeshttps://doi.org/10.1007/978-981-16-7487-7_7openalex-snapshot
A Modern Primer on Processing in Memory
inferred← citeshttps://doi.org/10.1007/s11227-019-02891-wopenalex-snapshot
Time-sensitivity-aware shared cache architecture for multi-core embedded systems
inferred← citeshttps://doi.org/10.1016/bs.adcom.2017.04.004openalex-snapshot
Simple Operations in Memory to Reduce Data Movement
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.jpdc.2019.01.005openalex-snapshot
Scheduling opportunities for asymmetrically reliable caches
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.01.009openalex-snapshot
Processing data where it makes sense: Enabling in-memory computation
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103832openalex-snapshot
InterStellar 2.0: Fine-grained stream–guided HW/SW co-design for multi-channel DRAM performance steering
inferred← citeshttps://doi.org/10.1109/access.2021.3070868openalex-snapshot
Energy Reduction Through Memory Aware Real-Time Scheduling on Virtual Machine in Multi-Cores Server
inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot
A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/cluster.2017.130openalex-snapshot
Utility-Based Hybrid Memory Management
inferred← citeshttps://doi.org/10.1109/dac.2018.8465877openalex-snapshot
FLOSS: FLOw Sensitive Scheduling on Mobile Platforms
inferred← citeshttps://doi.org/10.1109/fpl.2019.00049openalex-snapshot
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446095openalex-snapshot
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
inferred← citeshttps://doi.org/10.1109/hpca.2018.00026openalex-snapshot
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
inferred← citeshttps://doi.org/10.1109/hpca.2019.00011openalex-snapshot
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00037openalex-snapshot
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00048openalex-snapshot
Deadline-Aware Offloading for High-Throughput Accelerators
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00087openalex-snapshot
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
inferred← citeshttps://doi.org/10.1109/ic2e52221.2021.00020openalex-snapshot
Optimizing Goodput of Real-time Serverless Functions using Dynamic Slicing with vGPUs
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753327openalex-snapshot
A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance
inferred← citeshttps://doi.org/10.1109/icde53745.2022.00270openalex-snapshot
Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00030openalex-snapshot
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA
inferred← citeshttps://doi.org/10.1109/icpp.2017.42openalex-snapshot
A Dynamic Resource Controller for a Lambda Architecture
inferred← citeshttps://doi.org/10.1109/indin.2018.8471962openalex-snapshot
Deadline-aware Memory Scheduler and Governor for Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/ipdpsw.2017.37openalex-snapshot
Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/isca.2018.00025openalex-snapshot
Scheduling Page Table Walks for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1109/isca.2018.00041openalex-snapshot
FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00029openalex-snapshot
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00019openalex-snapshot
COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices
inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00037openalex-snapshot
Concurrent PIM and Load/Store Servicing in PIM-Enabled Memory
inferred← citeshttps://doi.org/10.1109/micro.2018.00032openalex-snapshot
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00036openalex-snapshot
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00088openalex-snapshot
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00072openalex-snapshot
BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads
inferred← citeshttps://doi.org/10.1109/socc.2018.8618555openalex-snapshot
Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup
inferred← citeshttps://doi.org/10.1109/sp40000.2020.00085openalex-snapshot
Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers
inferred← citeshttps://doi.org/10.1109/tc.2020.2970062openalex-snapshot
An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/tce.2018.2843287openalex-snapshot
Dynamic Transaction Management for System Level Quality-of-Service in Mobile APs
inferred← citeshttps://doi.org/10.1109/tmc.2018.2883619openalex-snapshot
Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties
inferred← citeshttps://doi.org/10.1109/tpds.2016.2526003openalex-snapshot
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling
inferred← citeshttps://doi.org/10.1109/tpds.2019.2906891openalex-snapshot
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication
inferred← citeshttps://doi.org/10.1109/vlsi-dat49148.2020.9196490openalex-snapshot
Intelligent Architectures for Intelligent Machines
inferred← citeshttps://doi.org/10.1142/s0218126618501268openalex-snapshot
Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers
inferred← citeshttps://doi.org/10.1145/2896377.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferred← citeshttps://doi.org/10.1145/2964791.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferred← citeshttps://doi.org/10.1145/2967938.2967940openalex-snapshot
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities
inferred← citeshttps://doi.org/10.1145/2990299.2990300openalex-snapshot
Rethinking memory system design
inferred← citeshttps://doi.org/10.1145/3007647openalex-snapshot
Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems
inferred← citeshttps://doi.org/10.1145/3014429openalex-snapshot
Aggregate Flow-Based Performance Fairness in CMPs
inferred← citeshttps://doi.org/10.1145/3078505.3078590openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferred← citeshttps://doi.org/10.1145/3084447openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferred← citeshttps://doi.org/10.1145/3123939.3123948openalex-snapshot
Race-to-sleep + content caching + display caching
inferred← citeshttps://doi.org/10.1145/3124451openalex-snapshot
Providing Predictable Performance via a Slowdown Estimation Model
inferred← citeshttps://doi.org/10.1145/3126540openalex-snapshot
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
inferred← citeshttps://doi.org/10.1145/3297663.3310305openalex-snapshot
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
inferred← citeshttps://doi.org/10.1145/3309697.3331482openalex-snapshot
Demystifying Complex Workload-DRAM Interactions
inferred← citeshttps://doi.org/10.1145/3319804openalex-snapshot
A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets
inferred← citeshttps://doi.org/10.1145/3326124openalex-snapshot
Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution
inferred← citeshttps://doi.org/10.1145/3366708openalex-snapshot
Demystifying Complex Workload-DRAM Interactions
inferred← citeshttps://doi.org/10.1145/3377149openalex-snapshot
Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding
inferred← citeshttps://doi.org/10.1145/3466823openalex-snapshot
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs
inferred← citeshttps://doi.org/10.1145/3534879.3534882openalex-snapshot
A Closer Look at Intel Resource Director Technology (RDT)
inferred← citeshttps://doi.org/10.1145/3757742openalex-snapshot
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators
inferred← citeshttps://doi.org/10.1145/3767110.3767122openalex-snapshot
Stream-Aware Intelligent Memory Controller through HW/SW Co-Design
inferred← citeshttps://doi.org/10.1177/10943420251347461openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
inferred← citeshttps://doi.org/10.1184/r1/6723512openalex-snapshot
Techniques for Shared Resource Management in Systems with Throughput Processors
inferred← citeshttps://doi.org/10.14288/1.0394065openalex-snapshot
Models and techniques for designing mobile system-on-chip devices
inferred← citeshttps://doi.org/10.1587/elex.16.20190351openalex-snapshot
IP-aware cache partition and replacement scheme for mobile computing devices
inferred← citeshttps://doi.org/10.1631/fitee.2200449openalex-snapshot
A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system
inferred← citeshttps://doi.org/10.2139/ssrn.5373047openalex-snapshot
Efficient Design and Interface for Unified Dram Memory in Shared Cpu-Gpu Address Spaces
inferred← citeshttps://doi.org/10.23919/date.2019.8714915openalex-snapshot
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474073openalex-snapshot
Intelligent Architectures for Intelligent Computing Systems
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774776openalex-snapshot
Thermal- and Cache-Aware Resource Management based on ML- Driven Cache Contention Prediction
inferred← citeshttps://doi.org/10.3390/electronics13173492openalex-snapshot
Enhancing QoS in Multicore Systems with Heterogeneous Memory Configurations
inferred← citeshttps://doi.org/10.3929/ethz-b-000519275openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.48550/arxiv.1601.06903openalex-snapshot
Tiered-Latency DRAM (TL-DRAM)
inferred← citeshttps://doi.org/10.48550/arxiv.1602.06005openalex-snapshot
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing
inferred← citeshttps://doi.org/10.48550/arxiv.1603.08454openalex-snapshot
Adaptive-Latency DRAM (AL-DRAM)
inferred← citeshttps://doi.org/10.48550/arxiv.1609.07234openalex-snapshot
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns
inferred← citeshttps://doi.org/10.48550/arxiv.1708.04911openalex-snapshot
Improving Multi-Application Concurrency Support Within the GPU Memory System
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11038openalex-snapshot
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
inferred← citeshttps://doi.org/10.48550/arxiv.1805.01966openalex-snapshot
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
inferred← citeshttps://doi.org/10.48550/arxiv.1805.02498openalex-snapshot
Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance
inferred← citeshttps://doi.org/10.48550/arxiv.1805.03154openalex-snapshot
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips
inferred← citeshttps://doi.org/10.48550/arxiv.1805.05926openalex-snapshot
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1902.07609openalex-snapshot
Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
inferred← citeshttps://doi.org/10.48550/arxiv.1903.03988openalex-snapshot
Processing Data Where It Makes Sense: Enabling In-Memory Computation
inferred← citeshttps://doi.org/10.48550/arxiv.2102.05981openalex-snapshot
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
inferred← citeshttps://doi.org/10.70675/ff9a8713ze4f9z421ez8b99zdfef9781d066openalex-snapshot
Towards compression at all levels in the memory hierarchy
inferred← citeshttps://doi.org/10.7282/t3-m0cq-tt95openalex-snapshot
Improving and complementing virtual memory using hardware techniques
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