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Memory Latency Reduction via Thread Throttling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-45937-5_14openalex-snapshot
StreamIt: A Language for Streaming Applications
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Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs
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Computer architecture: a quantitative approach
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Distinctive Image Features from Scale-Invariant Keypoints
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Imagine: media processing with streams
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Data and Computation Transformations for Brook Streaming Applications on Multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2005.26openalex-snapshot
Power Efficient Processor Architecture and The Cell Processor
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Improving effective bandwidth through compiler enhancement of global cache reuse
inferredcites →https://doi.org/10.1109/ipdps.2007.370234openalex-snapshot
Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution
inferredcites →https://doi.org/10.1109/ipdps.2009.5161013openalex-snapshot
Core-aware memory access scheduling schemes
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A bandwidth-efficient architecture for media processing
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Stream Programming on General-Purpose Processors
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Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
inferredcites →https://doi.org/10.1109/pact.2007.15openalex-snapshot
Architectural Support for the Stream Execution Model on General-Purpose Processors
inferredcites →https://doi.org/10.1109/pact.2007.29openalex-snapshot
Effective Management of DRAM Bandwidth in Multicore Processors
inferredcites →https://doi.org/10.1109/pact.2007.4336195openalex-snapshot
Architectural Support for the Stream Execution Model on General-Purpose Processors
inferredcites →https://doi.org/10.1109/pact.2007.4336216openalex-snapshot
Effective Management of DRAM Bandwidth in Multicore Processors
inferredcites →https://doi.org/10.1145/1152154.1152164openalex-snapshot
Compiling for stream processing
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1735970.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferredcites →https://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1736020.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferredcites →https://doi.org/10.1145/1736020.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1854273.1854306openalex-snapshot
On mitigating memory bandwidth contention through bandwidth-aware scheduling
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/357783.331677openalex-snapshot
The processor-memory bottleneck
inferredcites →https://doi.org/10.1145/605397.605428openalex-snapshot
A stream compiler for communication-exposed architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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State of the art and challenges for test and reliability of emerging nonvolatile resistive memories
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A Staged Memory Resource Management Method for CMP systems
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A Bandwidth-Optimized Multi-core Architecture for Irregular Applications
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MRPB: Memory request prioritization for massively parallel processors
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Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning
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MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks
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ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators
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Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model
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F2C2-STM: Flux-Based Feedback-Driven Concurrency Control for STMs
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XAMP: An eXtensible Analytical Model Platform
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Characterizing Cache-Asymmetric CPU Topologies on AMD 3D V-Cache Processors
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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs
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A Cache Aware Multithreading Decision Scheme on GPGPUs
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Cache-Conscious Wavefront Scheduling
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Adaptive Cache Management for Energy-Efficient GPU Computing
inferred← citeshttps://doi.org/10.1109/micro.2014.62openalex-snapshot
Managing GPU Concurrency in Heterogeneous Architectures
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Coordinate Memory Deduplication and Partition for Improving Performance in Cloud Computing
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FPS: A Fair-Progress Process Scheduling Policy on Shared-Memory Multiprocessors
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An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors
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Parallel application memory scheduling
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Trace-driven simulation of memory system scheduling in multithread application
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Providing fairness on shared-memory multiprocessors via process scheduling
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Providing fairness on shared-memory multiprocessors via process scheduling
inferred← citeshttps://doi.org/10.1145/2482767.2482774openalex-snapshot
Scheduling optimization in multicore multithreaded microprocessors through dynamic modeling
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Divergence-aware warp scheduling
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The Impact on the Performance of Co-running Virtual Machines in a Virtualized Environment
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