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Refresh pausing in DRAM memory systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/asic.2001.954696openalex-snapshot
Block-based multi-period refresh for energy efficient dynamic memory
inferredcites →https://doi.org/10.1109/hpca.2006.1598122openalex-snapshot
Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
inferredcites →https://doi.org/10.1109/hpca.2013.6522355openalex-snapshot
A case for Refresh Pausing in DRAM memory systems
inferredcites →https://doi.org/10.1109/isca.2008.16openalex-snapshot
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
inferredcites →https://doi.org/10.1109/micro.2007.13openalex-snapshot
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
inferredcites →https://doi.org/10.1109/micro.2007.38openalex-snapshot
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
inferredcites →https://doi.org/10.1109/micro.2010.22openalex-snapshot
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
inferredcites →https://doi.org/10.1109/ted.2011.2160066openalex-snapshot
Characterization of the Variable Retention Time in Dynamic Random Access Memory
inferredcites →https://doi.org/10.1145/1394608.1382127openalex-snapshot
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
inferredcites →https://doi.org/10.1145/1815961.1815973openalex-snapshot
Reducing cache power with low-cost, multi-bit error-correcting codes
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/300979.300998openalex-snapshot
A performance comparison of contemporary DRAM architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10854-018-0552-5openalex-snapshot
Point defect chemistry of donor-doped bismuth titanate ceramic
inferred← citeshttps://doi.org/10.1016/j.matpr.2017.07.030openalex-snapshot
RF-magnetron sputtering deposition of ultra-thin Hf 0.5 Zr 0.5 O 2 films for non-volatile memory applications
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.01.010openalex-snapshot
Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.11.007openalex-snapshot
Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme
inferred← citeshttps://doi.org/10.1016/j.vlsi.2017.06.011openalex-snapshot
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs
inferred← citeshttps://doi.org/10.1109/access.2024.3514377openalex-snapshot
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
inferred← citeshttps://doi.org/10.1109/cases.2015.7324549openalex-snapshot
Quality-aware data allocation in approximate DRAM
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070999openalex-snapshot
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
inferred← citeshttps://doi.org/10.1109/iolts.2017.8046197openalex-snapshot
Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms
inferred← citeshttps://doi.org/10.1109/ipdps.2016.58openalex-snapshot
Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00183openalex-snapshot
Early Silicon of Raptor: The First 3D-DRAM Accelerator for Generative Inference
inferred← citeshttps://doi.org/10.1109/mascots.2016.40openalex-snapshot
An Experimental Study on the Effect of Asymmetric Memory Latency of New Memory on Application Performance
inferred← citeshttps://doi.org/10.1109/micro.2018.00034openalex-snapshot
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00062openalex-snapshot
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00074openalex-snapshot
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations
inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184512openalex-snapshot
Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC
inferred← citeshttps://doi.org/10.1109/tc.2016.2640296openalex-snapshot
Quality Configurable Approximate DRAM
inferred← citeshttps://doi.org/10.1109/tim.2023.3309355openalex-snapshot
Constraint Models of SDRAM-Based Arbitrary Waveform Generator
inferred← citeshttps://doi.org/10.1145/2989081.2989103openalex-snapshot
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories
inferred← citeshttps://doi.org/10.1145/3132402.3132419openalex-snapshot
Using run-time reverse-engineering to optimize DRAM refresh
inferred← citeshttps://doi.org/10.1177/10943420251347461openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
inferred← citeshttps://doi.org/10.1587/transele.e101.c.170openalex-snapshot
Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
inferred← citeshttps://doi.org/10.3390/nano15151166openalex-snapshot
Binary-Weighted Neural Networks Using FeRAM Array for Low-Power AI Computing
inferred← citeshttps://doi.org/10.3844/jcssp.2023.1212.1221openalex-snapshot
Segment-Aware Dynamic Partitioning PCM-DRAM: A Solution to IoT Devices Development Constraints
inferred← citeshttps://doi.org/10.3929/ethz-b-000463029openalex-snapshot
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
inferred← citeshttps://doi.org/10.5555/2830689.2830702openalex-snapshot
Quality-aware data allocation in approximate DRAM
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