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Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-031-01724-7openalex-snapshot
The Memory System
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/ecrts.2010.23openalex-snapshot
Making DRAM Refresh Predictable
inferredcites →https://doi.org/10.1109/hpca.2001.903260openalex-snapshot
DRAM energy management using software and hardware directed power mode control
inferredcites →https://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferredcites →https://doi.org/10.1109/isscc.2004.1332666openalex-snapshot
An 800MHz embedded DRAM with a concurrent refresh mode
inferredcites →https://doi.org/10.1109/jssc.2005.848019openalex-snapshot
An 800-MHz embedded DRAM with a concurrent refresh mode
inferredcites →https://doi.org/10.1109/micro.2007.13openalex-snapshot
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
inferredcites →https://doi.org/10.1109/micro.2007.38openalex-snapshot
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1105734.1105748openalex-snapshot
DRAMsim
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/1669112.1669156openalex-snapshot
ESKIMO
inferredcites →https://doi.org/10.1145/339647.339668openalex-snapshot
Memory access scheduling
inferredcites →https://doi.org/10.1145/383082.383118openalex-snapshot
Memory controller policies for DRAM power management

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Forming‐Free Resistive Switching of Electrochemical Titanium Oxide Localized Nanostructures: Anodization, Chemical Composition, Nanoscale Size Effects, and Memristive Storage
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Charge-Aware DRAM Refresh Reduction with Value Transformation
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Intelligent Vision Systems: Exploring the State-of-the-Art and Opportunities for the Future
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Refresh Now and Then
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Versatile refresh
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Versatile refresh
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RAIDR
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PARDIS
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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
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An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
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ArchShield
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An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
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Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
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A programmable memory controller for the DDRx interfacing standards
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Refresh pausing in DRAM memory systems
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ANATOMY
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DTail
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Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency
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ANATOMY
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EFGR
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Reducing access latency of MLC PCMs through line striping
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Flexible auto-refresh
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Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes
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Omitting Refresh
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SPCM
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Flexible auto-refresh
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CLARA
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MicroRefresh
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Hardware-Software Co-design to Mitigate DRAM Refresh Overheads
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The Reach Profiler (REAPER)
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Hardware-Software Co-design to Mitigate DRAM Refresh Overheads
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Hardware-Software Co-design to Mitigate DRAM Refresh Overheads
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Hardware-Software Co-design to Mitigate DRAM Refresh Overheads
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Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
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Using run-time reverse-engineering to optimize DRAM refresh
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The Reach Profiler (REAPER)
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CACF
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CROW
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Demystifying Complex Workload-DRAM Interactions
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ReTagger
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Demystifying Complex Workload-DRAM Interactions
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Refresh Triggered Computation
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Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly
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Improving DRAM Performance by Parallelizing Refreshes with Accesses
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A Pre-Refresh Technique for Improving DRAM Performance
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A survey of architectural techniques for DRAM power management
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Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
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Addressing Processor Over-Provisioning on Large-Scale Multi-Core Platforms
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RBC: A memory architecture for improved performance and energy efficiency
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MRAM: A Versatile Non-Volatile Memory for Next-Generation Computing
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Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
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Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses
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Heterogeneous-Reliability Memory: Exploiting Application-Level Memory Error Tolerance
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Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
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Compiler assisted dynamic register file in GPGPU
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Cache memory design in the FinFET era
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Application-Specific Memory Subsystems
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