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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Dynamic Memory Design for Low Data-Retention Power
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Heterogeneous chip multiprocessors
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A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
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Die Stacking (3D) Microarchitecture
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Reunion: Complexity-Effective Multicore Redundancy
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What points at this work
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Compiler assisted dynamic register file in GPGPU
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95758openalex-snapshot
Cache memory design in the FinFET era
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