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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-90385-9_5openalex-snapshot

The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

inferredcites →https://doi.org/10.1007/s004460050028openalex-snapshot

Software transactional memory

inferredcites →https://doi.org/10.1016/j.micpro.2019.01.009openalex-snapshot

Processing data where it makes sense: Enabling in-memory computation

inferredcites →https://doi.org/10.1016/s0169-7552(98)00110-xopenalex-snapshot

The anatomy of a large-scale hypertextual Web search engine

inferredcites →https://doi.org/10.1109/40.592312openalex-snapshot

A case for intelligent RAM

inferredcites →https://doi.org/10.1109/5.747863openalex-snapshot

Cache-coherent distributed shared memory: perspectives on its development and future challenges

inferredcites →https://doi.org/10.1109/hpca.2001.903257openalex-snapshot

Automatically mapping code on an intelligent memory architecture

inferredcites →https://doi.org/10.1109/hpca.2005.41openalex-snapshot

Unbounded Transactional Memory

inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot

LogTM: Log-based Transactional Memory

inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers

inferredcites →https://doi.org/10.1109/hpca.2015.7056040openalex-snapshot

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

inferredcites →https://doi.org/10.1109/hpca.2017.37openalex-snapshot

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

inferredcites →https://doi.org/10.1109/hpca.2017.54openalex-snapshot

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

inferredcites →https://doi.org/10.1109/hpca.2018.00053openalex-snapshot

GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

inferredcites →https://doi.org/10.1109/iccd.2012.6378608openalex-snapshot

FlexRAM: Toward an advanced Intelligent Memory system

inferredcites →https://doi.org/10.1109/iccd.2016.7753257openalex-snapshot

Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

inferredcites →https://doi.org/10.1109/icde.2011.5767867openalex-snapshot

HyPer: A hybrid OLTP&OLAP main memory database system based on virtual memory snapshots

inferredcites →https://doi.org/10.1109/icde.2013.6544839openalex-snapshot

Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware

inferredcites →https://doi.org/10.1109/icde.2015.7113373openalex-snapshot

Oracle Database In-Memory: A dual format in-memory database

inferredcites →https://doi.org/10.1109/icpp.1994.108openalex-snapshot

EXECUBE-A New Architecture for Scaleable MPPs

inferredcites →https://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot

MachSuite: Benchmarks for accelerator design and customized architectures

inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot

Bulk Disambiguation of Speculative Threads in Multiprocessors

inferredcites →https://doi.org/10.1109/isca.2016.41openalex-snapshot

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory

inferredcites →https://doi.org/10.1109/isca.2016.46openalex-snapshot

Accelerating Dependent Cache Misses with an Enhanced Memory Controller

inferredcites →https://doi.org/10.1109/ispass.2014.6844483openalex-snapshot

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

inferredcites →https://doi.org/10.1109/ispass.2016.7482091openalex-snapshot

Observations and opportunities in architecting shared virtual memory for heterogeneous systems

inferredcites →https://doi.org/10.1109/lca.2015.2414456openalex-snapshot

Ramulator: A Fast and Extensible DRAM Simulator

inferredcites →https://doi.org/10.1109/lca.2015.2434872openalex-snapshot

Fast Bulk Bitwise AND and OR in DRAM

inferredcites →https://doi.org/10.1109/lca.2016.2577557openalex-snapshot

LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory

inferredcites →https://doi.org/10.1109/mc.2015.374openalex-snapshot

Computing beyond Moore's Law

inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

inferredcites →https://doi.org/10.1109/micro.2012.49openalex-snapshot

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

inferredcites →https://doi.org/10.1109/micro.2018.00058openalex-snapshot

Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

inferredcites →https://doi.org/10.1109/micro.2018.00059openalex-snapshot

Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach

inferredcites →https://doi.org/10.1109/mm.2011.89openalex-snapshot

GPUs and the Future of Parallel Computing

inferredcites →https://doi.org/10.1109/mm.2016.9openalex-snapshot

Near-Memory Data Services

inferredcites →https://doi.org/10.1109/pact.2013.6618812openalex-snapshot

Memory-centric system interconnect design with Hybrid Memory Cubes

inferredcites →https://doi.org/10.1109/pact.2015.22openalex-snapshot

Practical Near-Data Processing for In-Memory Analytics Frameworks

inferredcites →https://doi.org/10.1109/pact.2017.56openalex-snapshot

Near-Memory Address Translation

inferredcites →https://doi.org/10.1109/perser.2005.1506430openalex-snapshot

Implementing kilo-instruction multiprocessors

inferredcites →https://doi.org/10.1109/tc.1970.5008902openalex-snapshot

A Logic-in-Memory Computer

inferredcites →https://doi.org/10.1109/tpds.2005.4openalex-snapshot

A two-level directory architecture for highly scalable cc-NUMA multiprocessors

inferredcites →https://doi.org/10.1109/vlsit.2012.6242474openalex-snapshot

Hybrid memory cube new DRAM architecture increases density and performance

inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot

Transactional Memory Coherence and Consistency

inferredcites →https://doi.org/10.1145/1150019.1136506openalex-snapshot

Bulk Disambiguation of Speculative Threads in Multiprocessors

inferredcites →https://doi.org/10.1145/1250662.1250696openalex-snapshot

Mechanisms for store-wait-free multiprocessors

inferredcites →https://doi.org/10.1145/1250662.1250697openalex-snapshot

BulkSC

inferredcites →https://doi.org/10.1145/1508244.1508255openalex-snapshot

DMP

inferredcites →https://doi.org/10.1145/165123.165164openalex-snapshot

Transactional memory

inferredcites →https://doi.org/10.1145/1854273.1854291openalex-snapshot

WAYPOINT

inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot

Dark silicon and the end of multicore scaling

inferredcites →https://doi.org/10.1145/2024716.2024718openalex-snapshot

The gem5 simulator

inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot

Reducing memory interference in multicore systems via application-aware memory channel partitioning

inferredcites →https://doi.org/10.1145/2442516.2442530openalex-snapshot

Ligra

inferredcites →https://doi.org/10.1145/2485922.2485926openalex-snapshot

Thin servers with smart pipes

inferredcites →https://doi.org/10.1145/2540708.2540725openalex-snapshot

RowClone

inferredcites →https://doi.org/10.1145/2540708.2540747openalex-snapshot

Heterogeneous system coherence for integrated CPU-GPU systems

inferredcites →https://doi.org/10.1145/2540708.2540748openalex-snapshot

Meet the walkers

inferredcites →https://doi.org/10.1145/2541940.2541961openalex-snapshot

Q100

inferredcites →https://doi.org/10.1145/2588555.2612174openalex-snapshot

Histograms as a side effect of data movement for big data

inferredcites →https://doi.org/10.1145/2600212.2600213openalex-snapshot

TOP-PIM

inferredcites →https://doi.org/10.1145/2600212.2600222openalex-snapshot

Seraph

inferredcites →https://doi.org/10.1145/2678373.2665697openalex-snapshot

The dirty-block index

inferredcites →https://doi.org/10.1145/2678373.2665749openalex-snapshot

WebCore

inferredcites →https://doi.org/10.1145/2694344.2694350openalex-snapshot

Synchronization Using Remote-Scope Promotion

inferredcites →https://doi.org/10.1145/2749469.2750385openalex-snapshot

PIM-enabled instructions

inferredcites →https://doi.org/10.1145/2749469.2750386openalex-snapshot

A scalable processing-in-memory accelerator for parallel graph processing

inferredcites →https://doi.org/10.1145/2749469.2750397openalex-snapshot

Data reorganization in memory using 3D-stacked DRAM

inferredcites →https://doi.org/10.1145/2749469.2750421openalex-snapshot

Fusion

inferredcites →https://doi.org/10.1145/2771937.2771945openalex-snapshot

Beyond the Wall

inferredcites →https://doi.org/10.1145/277830.277852openalex-snapshot

Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor

inferredcites →https://doi.org/10.1145/279358.279387openalex-snapshot

Active pages: a computation model for intelligent memory

inferredcites →https://doi.org/10.1145/2830772.2830800openalex-snapshot

DeSC

inferredcites →https://doi.org/10.1145/2830772.2830821openalex-snapshot

Efficient GPU synchronization without scopes

inferredcites →https://doi.org/10.1145/2832911openalex-snapshot

Simultaneous Multi-Layer Access

inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot

Using cache memory to reduce processor-memory traffic

inferredcites →https://doi.org/10.1145/285930.285987openalex-snapshot

A low-overhead coherence solution for multiprocessors with private cache memories

inferredcites →https://doi.org/10.1145/2882903.2915231openalex-snapshot

Bridging the Archipelago between Row-Stores and Column-Stores for Hybrid Workloads

inferredcites →https://doi.org/10.1145/291069.291020openalex-snapshot

Data speculation support for a chip multiprocessor

inferredcites →https://doi.org/10.1145/2967938.2967940openalex-snapshot

Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities

inferredcites →https://doi.org/10.1145/2967938.2967958openalex-snapshot

Accelerating Linked-list Traversal Through Near-Data Processing

inferredcites →https://doi.org/10.1145/3007787.3001159openalex-snapshot

Transparent offloading and mapping (TOM)

inferredcites →https://doi.org/10.1145/3007787.3001178openalex-snapshot

Neurocube

inferredcites →https://doi.org/10.1145/3007787.3001184openalex-snapshot

Accelerating dependent cache misses with an enhanced memory controller

inferredcites →https://doi.org/10.1145/3035918.3035959openalex-snapshot

BatchDB

inferredcites →https://doi.org/10.1145/3037697.3037702openalex-snapshot

TETRIS

inferredcites →https://doi.org/10.1145/3037697.3037715openalex-snapshot

Crossing Guard

inferredcites →https://doi.org/10.1145/3037697.3037736openalex-snapshot

Mallacc

inferredcites →https://doi.org/10.1145/3079856.3080233openalex-snapshot

The Mondrian Data Engine

inferredcites →https://doi.org/10.1145/3079856.3080234openalex-snapshot

Architectural Support for Server-Side PHP Processing

inferredcites →https://doi.org/10.1145/3123939.3123941openalex-snapshot

IDEAL

inferredcites →https://doi.org/10.1145/3123939.3123954openalex-snapshot

Data movement aware computation partitioning

inferredcites →https://doi.org/10.1145/3123939.3123983openalex-snapshot

UDP

inferredcites →https://doi.org/10.1145/3123939.3124544openalex-snapshot

Ambit

inferredcites →https://doi.org/10.1145/3126908.3126918openalex-snapshot

Leveraging near data processing for high-performance checkpoint/restart

inferredcites →https://doi.org/10.1145/3126908.3126965openalex-snapshot

Toward standardized near-data processing with unrestricted data placement for GPUs

inferredcites →https://doi.org/10.1145/3155287openalex-snapshot

CAIRO

inferredcites →https://doi.org/10.1145/3173162.3173177openalex-snapshot

Google Workloads for Consumer Devices

inferredcites →https://doi.org/10.1145/319566.319567openalex-snapshot

On optimistic methods for concurrency control

inferredcites →https://doi.org/10.1145/3299874.3322805openalex-snapshot

Processing Data Where It Makes Sense in Modern Computing Systems

inferredcites →https://doi.org/10.1145/3309697.3331482openalex-snapshot

Demystifying Complex Workload-DRAM Interactions

inferredcites →https://doi.org/10.1145/3316781.3317867openalex-snapshot

NAPEL

inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot

A scalable approach to thread-level speculation

inferredcites →https://doi.org/10.1145/339647.339673openalex-snapshot

Smart Memories

inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot

Space/time trade-offs in hash coding with allowable errors

inferredcites →https://doi.org/10.1145/514191.514197openalex-snapshot

The architecture of the DIVA processing-in-memory chip

inferredcites →https://doi.org/10.1145/605397.605400openalex-snapshot

Speculative synchronization

inferredcites →https://doi.org/10.1145/800015.808204openalex-snapshot

A low-overhead coherence solution for multiprocessors with private cache memories

inferredcites →https://doi.org/10.1145/800046.801647openalex-snapshot

Using cache memory to reduce processor-memory traffic

inferredcites →https://doi.org/10.1147/jrd.2014.2380198openalex-snapshot

CAPI: A Coherent Accelerator Processor Interface

inferredcites →https://doi.org/10.14778/2856318.2856321openalex-snapshot

Asynchronous memory access chaining

inferredcites →https://doi.org/10.48550/arxiv.1506.03160openalex-snapshot

Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface

inferredcites →https://doi.org/10.48550/arxiv.1706.03162openalex-snapshot

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures

inferredcites →https://doi.org/10.48550/arxiv.1902.07609openalex-snapshot

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study

inferredcites →https://doi.org/10.5555/1331699.1331713openalex-snapshot

Implementing Signatures for Transactional Memory

inferredcites →https://doi.org/10.5555/3195638.3195669openalex-snapshot

Lazy release consistency for GPUs

inferredcites →https://doi.org/10.5555/3195638.3195692openalex-snapshot

HARE: hardware accelerator for regular expressions

inferredcites →https://doi.org/10.5555/3195638.3195707openalex-snapshot

Graphicionado: a high-performance and energy-efficient accelerator for graph analytics

inferredcites →https://doi.org/10.5555/563998.564036openalex-snapshot

Speculative lock elision: enabling highly concurrent multithreaded execution

inferredcites →https://doi.org/10.5555/774861.774871openalex-snapshot

Master/Slave Speculative Parallelization

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.5281/zenodo.6942162openalex-extracted

inferred← citeshttps://doi.org/10.1007/978-3-030-98781-7_7openalex-snapshot

PIM Software Stack

inferred← citeshttps://doi.org/10.1007/978-981-15-8135-9_6openalex-snapshot

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks

inferred← citeshttps://doi.org/10.1007/978-981-16-7487-7_7openalex-snapshot

A Modern Primer on Processing in Memory

inferred← citeshttps://doi.org/10.1007/978-981-19-1012-8_36openalex-snapshot

Barriers to the Widespread Adoption of Processing-in-Memory Architectures

inferred← citeshttps://doi.org/10.1007/978-981-99-4764-5_18openalex-snapshot

An HBM3 Processing-In-Memory Architecture for Security and Data Integrity: Case Study

inferred← citeshttps://doi.org/10.1007/s00778-025-00937-5openalex-snapshot

PIM-tree: A Skew-resistant Index for Processing-in-Memory

inferred← citeshttps://doi.org/10.1007/s11265-025-01974-7openalex-snapshot

An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons

inferred← citeshttps://doi.org/10.1007/s11432-020-3227-1openalex-snapshot

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

inferred← citeshttps://doi.org/10.1016/j.memori.2023.100051openalex-snapshot

A review on computational storage devices and near memory computing for high performance applications

inferred← citeshttps://doi.org/10.1016/j.memori.2025.100132openalex-snapshot

Multi armed bandit based resource allocation in Near Memory Processing architectures

inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102868openalex-snapshot

Near-memory computing: Past, present, and future

inferred← citeshttps://doi.org/10.1016/j.suscom.2024.101047openalex-snapshot

Nearest data processing in GPU

inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103481openalex-snapshot

BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures

inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

inferred← citeshttps://doi.org/10.1109/access.2022.3174101openalex-snapshot

Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

inferred← citeshttps://doi.org/10.1109/access.2023.3252002openalex-snapshot

Casper: Accelerating Stencil Computations Using Near-Cache Processing

inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247896openalex-snapshot

Lightning Talk: Memory-Centric Computing

inferred← citeshttps://doi.org/10.1109/dsn58291.2024.00024openalex-snapshot

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis

inferred← citeshttps://doi.org/10.1109/dsn64029.2025.00018openalex-snapshot

Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory

inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00014openalex-snapshot

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00031openalex-snapshot

SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00032openalex-snapshot

Near-Stream Computing: General and Transparent Near-Cache Acceleration

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00024openalex-snapshot

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00029openalex-snapshot

Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00083openalex-snapshot

Data Motion Acceleration: Chaining Cross-Domain Multi Accelerators

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408437openalex-snapshot

Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408588openalex-snapshot

PIM-Malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures

inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323777openalex-snapshot

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions

inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00035openalex-snapshot

NATSA: A Near-Data Processing Accelerator for Time Series Analysis

inferred← citeshttps://doi.org/10.1109/iccd63220.2024.00091openalex-snapshot

AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System

inferred← citeshttps://doi.org/10.1109/icetci57876.2023.10176861openalex-snapshot

A lightweight distributed processing computer system

inferred← citeshttps://doi.org/10.1109/igsc54211.2021.9651614openalex-snapshot

Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-In-Memory Hardware

inferred← citeshttps://doi.org/10.1109/isca45697.2020.00071openalex-snapshot

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture

inferred← citeshttps://doi.org/10.1109/isca45697.2020.00072openalex-snapshot

Near Data Acceleration with Concurrent Host Access

inferred← citeshttps://doi.org/10.1109/isca52012.2021.00045openalex-snapshot

CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations

inferred← citeshttps://doi.org/10.1109/isca52012.2021.00078openalex-snapshot

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

inferred← citeshttps://doi.org/10.1109/islped52811.2021.9502483openalex-snapshot

CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications

inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00013openalex-snapshot

Evaluating Machine LearningWorkloads on Memory-Centric Computing Systems

inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00031openalex-snapshot

TransPimLib: Efficient Transcendental Functions for Processing-in-Memory Systems

inferred← citeshttps://doi.org/10.1109/isvlsi54635.2022.00060openalex-snapshot

Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases

inferred← citeshttps://doi.org/10.1109/isvlsi54635.2022.00061openalex-snapshot

Exploiting Near-Data Processing to Accelerate Time Series Analysis

inferred← citeshttps://doi.org/10.1109/isvlsi54635.2022.00064openalex-snapshot

Machine Learning Training on a Real Processing-in-Memory System

inferred← citeshttps://doi.org/10.1109/lca.2021.3061905openalex-snapshot

MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator

inferred← citeshttps://doi.org/10.1109/lca.2023.3269399openalex-snapshot

Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

inferred← citeshttps://doi.org/10.1109/micro50266.2020.00081openalex-snapshot

GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis

inferred← citeshttps://doi.org/10.1109/micro56248.2022.00067openalex-snapshot

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

inferred← citeshttps://doi.org/10.1109/micro61859.2024.00053openalex-snapshot

PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems

inferred← citeshttps://doi.org/10.1109/pact52795.2021.00019openalex-snapshot

Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks

inferred← citeshttps://doi.org/10.1109/pact58117.2023.00029openalex-snapshot

Architecture-Aware Currying

inferred← citeshttps://doi.org/10.1109/pact65351.2025.00047openalex-snapshot

POSTER: DaPPA: A Data-Parallel Programming Framework for Processing-in-Memory Architectures

inferred← citeshttps://doi.org/10.1109/pact65351.2025.00050openalex-snapshot

POSTER: PIMAP: Characterizing a Real Processing-in-Memory System for Analytical Data Processing

inferred← citeshttps://doi.org/10.1109/tc.2021.3063378openalex-snapshot

Computing En-Route for Near-Data Processing

inferred← citeshttps://doi.org/10.1109/tc.2023.3243881openalex-snapshot

Operand-Oriented Virtual Memory Support for Near-Memory Processing

inferred← citeshttps://doi.org/10.1109/tcc.2022.3207145openalex-snapshot

SE-PIM: In-Memory Acceleration of Data-Intensive Confidential Computing

inferred← citeshttps://doi.org/10.1109/tetc.2022.3226132openalex-snapshot

ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems

inferred← citeshttps://doi.org/10.1109/tpds.2023.3297595openalex-snapshot

A Survey of Memory-Centric Energy Efficient Computer Architecture

inferred← citeshttps://doi.org/10.1109/vlsi-dat49148.2020.9196490openalex-snapshot

Intelligent Architectures for Intelligent Machines

inferred← citeshttps://doi.org/10.1111/psyp.14265openalex-snapshot

Multiverse analyses of fear acquisition and extinction retention in posttraumatic stress disorder

inferred← citeshttps://doi.org/10.1145/3316781.3323476openalex-snapshot

Enabling Practical Processing in and near Memory for Data-Intensive Computing

inferred← citeshttps://doi.org/10.1145/3357526.3357570openalex-snapshot

Attacking memory-hard scrypt with near-data-processing

inferred← citeshttps://doi.org/10.1145/3445814.3446749openalex-snapshot

SIMDRAM: a framework for bit-serial SIMD processing using DRAM

inferred← citeshttps://doi.org/10.1145/3503222.3507758openalex-snapshot

GPM: leveraging persistent memory from a GPU

inferred← citeshttps://doi.org/10.1145/3544974openalex-snapshot

A Survey on Memory-centric Computer Architectures

inferred← citeshttps://doi.org/10.1145/3558481.3591070openalex-snapshot

PIM-trie: A Skew-resistant Trie for Processing-in-Memory

inferred← citeshttps://doi.org/10.1145/3563697openalex-snapshot

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

inferred← citeshttps://doi.org/10.1145/3565053.3565054openalex-snapshot

Evaluating HPC Kernels for Processing in Memory

inferred← citeshttps://doi.org/10.1145/3583781.3590294openalex-snapshot

DrPIM: An Adaptive and Less-blocking Data Replication Framework for Processing-in-Memory Architecture

inferred← citeshttps://doi.org/10.1145/3613424.3623776openalex-snapshot

XFM: Accelerated Software-Defined Far Memory

inferred← citeshttps://doi.org/10.1145/3620665.3640376openalex-snapshot

PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization

inferred← citeshttps://doi.org/10.1145/3656019.3676947openalex-snapshot

PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System

inferred← citeshttps://doi.org/10.1145/3669940.3707253openalex-snapshot

pulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory

inferred← citeshttps://doi.org/10.1145/3695794.3695795openalex-snapshot

PIM-Potential: Broadening the Acceleration Reach of PIM Architectures

inferred← citeshttps://doi.org/10.1145/3763790openalex-snapshot

CCKit: An open-source toolkit for cache coherent accelerators

inferred← citeshttps://doi.org/10.1145/3833426openalex-snapshot

GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages

inferred← citeshttps://doi.org/10.1147/jrd.2019.2934048openalex-snapshot

Processing-in-memory: A workload-driven perspective

inferred← citeshttps://doi.org/10.21769/bioprotoc.5857openalex-snapshot

A Batch-Processing Pipeline for RNA-seq Gene Abundance Estimation

inferred← citeshttps://doi.org/10.23919/date51398.2021.9474073openalex-snapshot

Intelligent Architectures for Intelligent Computing Systems

inferred← citeshttps://doi.org/10.23919/date64628.2025.10993222openalex-snapshot

NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table

inferred← citeshttps://doi.org/10.3929/ethz-b-000519275openalex-snapshot

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

inferred← citeshttps://doi.org/10.48550/arxiv.1907.12947openalex-snapshot

A Workload and Programming Ease Driven Perspective of Processing-in-Memory

inferred← citeshttps://doi.org/10.48550/arxiv.1908.06362openalex-snapshot

Near Data Acceleration with Concurrent Host Access

inferred← citeshttps://doi.org/10.48550/arxiv.2103.00768openalex-snapshot

Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models

inferred← citeshttps://doi.org/10.48550/arxiv.2103.00798openalex-snapshot

Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design

inferred← citeshttps://doi.org/10.48550/arxiv.2104.08335openalex-snapshot

Demystifying BERT: Implications for Accelerator Design

inferred← citeshttps://doi.org/10.48550/arxiv.2105.03814openalex-snapshot

Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

inferred← citeshttps://doi.org/10.48550/arxiv.2105.12839openalex-snapshot

SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM

inferred← citeshttps://doi.org/10.48550/arxiv.2111.01916openalex-snapshot

Accelerating Genome Sequence Analysis via Efficient Hardware/Algorithm Co-Design

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