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FPGA HLS Today: Successes, Challenges, and Opportunities
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4842-5574-2openalex-snapshot
Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL
inferredcites →https://doi.org/10.1007/978-3-030-58568-6_9openalex-snapshot
ReActNet: Towards Precise Binary Neural Network with Generalized Activation Functions
inferredcites →https://doi.org/10.1007/978-3-319-26408-0_8openalex-snapshot
Source-to-Source Optimization for HLS
inferredcites →https://doi.org/10.1007/978-981-13-6037-4_8openalex-snapshot
Informatics for PacBio Long Reads
inferredcites →https://doi.org/10.1016/j.scico.2007.01.015openalex-snapshot
The Daikon system for dynamic detection of likely invariants
inferredcites →https://doi.org/10.1016/j.ygeno.2010.03.001openalex-snapshot
Assembly algorithms for next-generation sequencing data
inferredcites →https://doi.org/10.1093/bfgp/elr035openalex-snapshot
Comparison of the two major classes of assembly algorithms: overlap-layout-consensus and de-bruijn-graph
inferredcites →https://doi.org/10.1093/bioinformatics/bty191openalex-snapshot
Minimap2: pairwise alignment for nucleotide sequences
inferredcites →https://doi.org/10.1109/access.2020.3024098openalex-snapshot
Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains
inferredcites →https://doi.org/10.1109/asap.2016.7760777openalex-snapshot
Synthesisable recursion for C++ HLS tools
inferredcites →https://doi.org/10.1109/cases.2013.6662524openalex-snapshot
From software to accelerators with LegUp high-level synthesis
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/cgo.2009.20openalex-snapshot
Software Pipelined Execution of Stream Programs on GPUs
inferredcites →https://doi.org/10.1109/cgo51591.2021.9370308openalex-snapshot
MLIR: Scaling Compiler Infrastructure for Domain Specific Computation
inferredcites →https://doi.org/10.1109/conecct.2018.8482378openalex-snapshot
ReneGENE-DP: Accelerated Parallel Dynamic Programming for Genome Informatics
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/cvpr.2018.00474openalex-snapshot
MobileNetV2: Inverted Residuals and Linear Bottlenecks
inferredcites →https://doi.org/10.1109/cvpr.2018.00716openalex-snapshot
ShuffleNet: An Extremely Efficient Convolutional Neural Network for Mobile Devices
inferredcites →https://doi.org/10.1109/dac.2005.193931openalex-snapshot
MiniBit: bit-width optimization via affine arithmetic
inferredcites →https://doi.org/10.1109/dac.2018.8465827openalex-snapshot
S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters
inferredcites →https://doi.org/10.1109/dac18072.2020.9218718openalex-snapshot
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
inferredcites →https://doi.org/10.1109/fccm.2012.36openalex-snapshot
Hardware Acceleration of Short Read Mapping
inferredcites →https://doi.org/10.1109/fccm.2013.57openalex-snapshot
Reconfigurable Acceleration of Short Read Mapping
inferredcites →https://doi.org/10.1109/fccm.2014.15openalex-snapshot
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation
inferredcites →https://doi.org/10.1109/fccm.2014.48openalex-snapshot
FPGA Implementation of EM Algorithm for 3D CT Reconstruction
inferredcites →https://doi.org/10.1109/fccm.2015.27openalex-snapshot
A Novel High-Throughput Acceleration Engine for Read Alignment
inferredcites →https://doi.org/10.1109/fccm.2016.26openalex-snapshot
SynADT: Dynamic Data Structures in High Level Synthesis
inferredcites →https://doi.org/10.1109/fccm.2016.42openalex-snapshot
Acceleration of the Pair-HMM Algorithm for DNA Variant Calling
inferredcites →https://doi.org/10.1109/fccm.2017.25openalex-snapshot
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
inferredcites →https://doi.org/10.1109/fccm.2017.43openalex-snapshot
Customizing Neural Networks for Efficient FPGA Implementation
inferredcites →https://doi.org/10.1109/fccm.2017.44openalex-snapshot
HLScope: High-Level Performance Debugging for FPGA Designs
inferredcites →https://doi.org/10.1109/fccm.2018.00029openalex-snapshot
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
inferredcites →https://doi.org/10.1109/fccm.2018.00040openalex-snapshot
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing
inferredcites →https://doi.org/10.1109/fccm.2019.00027openalex-snapshot
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU
inferredcites →https://doi.org/10.1109/fccm.2019.00033openalex-snapshot
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations
inferredcites →https://doi.org/10.1109/fccm.2019.00038openalex-snapshot
Templatised Soft Floating-Point for High-Level Synthesis
inferredcites →https://doi.org/10.1109/fccm.2019.00058openalex-snapshot
A Scalable OpenCL-Based FPGA Accelerator for YOLOv2
inferredcites →https://doi.org/10.1109/fccm.2019.00078openalex-snapshot
Large-Scale and High-Throughput QR Decomposition on an FPGA
inferredcites →https://doi.org/10.1109/fccm48280.2020.00016openalex-snapshot
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark
inferredcites →https://doi.org/10.1109/fccm48280.2020.00017openalex-snapshot
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme
inferredcites →https://doi.org/10.1109/fccm48280.2020.00029openalex-snapshot
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit
inferredcites →https://doi.org/10.1109/fccm48280.2020.00064openalex-snapshot
Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing
inferredcites →https://doi.org/10.1109/fccm51124.2021.00020openalex-snapshot
FANS: FPGA-Accelerated Near-Storage Sorting
inferredcites →https://doi.org/10.1109/fccm51124.2021.00032openalex-snapshot
Extending High-Level Synthesis for Task-Parallel Programs
inferredcites →https://doi.org/10.1109/fpl.2014.6927413openalex-snapshot
A scalable, high-performance customized priority queue
inferredcites →https://doi.org/10.1109/fpl.2014.6927499openalex-snapshot
Hardware accelerated novel optical de novo assembly for large-scale genomes
inferredcites →https://doi.org/10.1109/fpl.2018.00077openalex-snapshot
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration
inferredcites →https://doi.org/10.1109/fpl.2019.00057openalex-snapshot
A Dynamic Memory Allocation Library for High-Level Synthesis
inferredcites →https://doi.org/10.1109/fpl50879.2020.00044openalex-snapshot
Precise Pointer Analysis in High-Level Synthesis
inferredcites →https://doi.org/10.1109/hcs52781.2021.9567229openalex-snapshot
ENIAD: A Reconfigurable Near-data Processing Architecture for Web-Scale AI-enriched Big Data Service
inferredcites →https://doi.org/10.1109/hotchips.2019.8875639openalex-snapshot
Xilinx First 7nm Device: Versal AI Core (VC1902)
inferredcites →https://doi.org/10.1109/hpca.2019.00044openalex-snapshot
FPGA Accelerated INDEL Realignment in the Cloud
inferredcites →https://doi.org/10.1109/hpec.2016.7761646openalex-snapshot
Mathematical foundations of the GraphBLAS
inferredcites →https://doi.org/10.1109/iccad.2013.6691121openalex-snapshot
SDC-based modulo scheduling for pipeline synthesis
inferredcites →https://doi.org/10.1109/iccad.2017.8203844openalex-snapshot
HLScope+,: Fast and accurate performance estimation for FPGA HLS
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942177openalex-snapshot
What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
inferredcites →https://doi.org/10.1109/iccad51958.2021.9643582openalex-snapshot
GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
inferredcites →https://doi.org/10.1109/ieeestd.1994.121433openalex-snapshot
IEEE Standard VHDL Language Reference Manual.
inferredcites →https://doi.org/10.1109/ieeestd.1996.81542openalex-snapshot
IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language
inferredcites →https://doi.org/10.1109/ipdpsw.2015.130openalex-snapshot
Accelerating Large-Scale Single-Source Shortest Path on FPGA
inferredcites →https://doi.org/10.1109/isca45697.2020.00031openalex-snapshot
Genesis: A Hardware Acceleration Framework for Genomic Data Analysis
inferredcites →https://doi.org/10.1109/isca52012.2021.00038openalex-snapshot
Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees
inferredcites →https://doi.org/10.1109/iscas.2019.8702260openalex-snapshot
Halide and GENESIS for Generating Domain-Specific Architecture of Guided Image Filtering
inferredcites →https://doi.org/10.1109/mcas.2021.3071631openalex-snapshot
Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits
inferredcites →https://doi.org/10.1109/mdat.2013.2293757openalex-snapshot
A Review of Hardware Acceleration for Computational Genomics
inferredcites →https://doi.org/10.1109/mm.2011.68openalex-snapshot
Implementing Domain-Specific Languages for Heterogeneous Parallel Computing
inferredcites →https://doi.org/10.1109/mm.2018.022071131openalex-snapshot
Serving DNNs in Real Time at Datacenter Scale with Project Brainwave
inferredcites →https://doi.org/10.1109/reconfig.2015.7393332openalex-snapshot
Optimizing memory performance for FPGA implementation of pagerank
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot
A Survey and Evaluation of FPGA High-Level Synthesis Tools
inferredcites →https://doi.org/10.1109/tcad.2017.2785257openalex-snapshot
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tcad.2018.2857040openalex-snapshot
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcsvt.2012.2221191openalex-snapshot
Overview of the High Efficiency Video Coding (HEVC) Standard
inferredcites →https://doi.org/10.1109/tpds.2019.2910068openalex-snapshot
HitGraph: High-throughput Graph Processing Framework on FPGA
inferredcites →https://doi.org/10.1109/tpds.2020.3039409openalex-snapshot
Transformations of High-Level Synthesis Codes for High-Performance Computing
inferredcites →https://doi.org/10.1109/tvlsi.2017.2720623openalex-snapshot
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs
inferredcites →https://doi.org/10.1145/1146909.1147025openalex-snapshot
An efficient and versatile scheduling algorithm based on SDC formulation
inferredcites →https://doi.org/10.1145/1929943.1929947openalex-snapshot
Automatic memory partitioning and scheduling for throughput and power optimization
inferredcites →https://doi.org/10.1145/2435264.2435273openalex-snapshot
Polyhedral-based data reuse optimization for configurable computing
inferredcites →https://doi.org/10.1145/2554688.2554780openalex-snapshot
Theory and algorithm for generalized memory partitioning in high-level synthesis
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847274openalex-snapshot
High Level Synthesis of Complex Applications
inferredcites →https://doi.org/10.1145/2847263.2847276openalex-snapshot
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3020078.3021698openalex-snapshot
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021730openalex-snapshot
Energy Efficient Scientific Computing on FPGAs using OpenCL
inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot
An OpenCL™ Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.1145/3020078.3021741openalex-snapshot
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
inferredcites →https://doi.org/10.1145/3020078.3021787openalex-snapshot
CPU-FPGA Co-Optimization for Big Data Applications
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3107953openalex-snapshot
Programming Heterogeneous Systems from an Image Processing DSL
inferredcites →https://doi.org/10.1145/3174243.3174245openalex-snapshot
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform
inferredcites →https://doi.org/10.1145/3174243.3174248openalex-snapshot
Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL
inferredcites →https://doi.org/10.1145/3195970.3199846openalex-snapshot
A modular digital VLSI flow for high-productivity SoC design
inferredcites →https://doi.org/10.1145/3373087.3375298openalex-snapshot
Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization
inferredcites →https://doi.org/10.1145/3373087.3375300openalex-snapshot
Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator
inferredcites →https://doi.org/10.1145/3373087.3375321openalex-snapshot
End-to-End Optimization of Deep Learning Applications
inferredcites →https://doi.org/10.1145/3394885.3431548openalex-snapshot
A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA
inferredcites →https://doi.org/10.1145/3431920.3439291openalex-snapshot
A Framework for Customizable FPGA-based Image Registration Accelerators
inferredcites →https://doi.org/10.1145/3431920.3439296openalex-snapshot
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
inferredcites →https://doi.org/10.1145/3431920.3439298openalex-snapshot
NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD
inferredcites →https://doi.org/10.1145/3431920.3439478openalex-snapshot
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow
inferredcites →https://doi.org/10.1145/3445814.3446712openalex-snapshot
A compiler infrastructure for accelerator generators
inferredcites →https://doi.org/10.1145/3469660openalex-snapshot
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
inferredcites →https://doi.org/10.1145/3490422.3502357openalex-snapshot
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
inferredcites →https://doi.org/10.1145/3490422.3502358openalex-snapshot
Accelerating SSSP for Power-Law Graphs
inferredcites →https://doi.org/10.1145/3494534openalex-snapshot
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
inferredcites →https://doi.org/10.1145/358438.349317openalex-snapshot
Bidwidth analysis with application to silicon compilation
inferredcites →https://doi.org/10.1186/s12864-019-5475-xopenalex-snapshot
Improving the sensitivity of long read overlap detection using grouped short k-mer matches
inferredcites →https://doi.org/10.48550/arxiv.1704.04760openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.48550/arxiv.1802.04799openalex-snapshot
TVM: An Automated End-to-End Optimizing Compiler for Deep Learning
inferredcites →https://doi.org/10.48550/arxiv.1807.01340openalex-snapshot
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
inferredcites →https://doi.org/10.48550/arxiv.1904.04421openalex-snapshot
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge
inferredcites →https://doi.org/10.48550/arxiv.1910.04436openalex-snapshot
hlslib: Software Engineering for Hardware Design
inferredcites →https://doi.org/10.48550/arxiv.2009.14381openalex-snapshot
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
inferredcites →https://doi.org/10.5555/2387880.2387883openalex-snapshot
PowerGraph: distributed graph-parallel computation on natural graphs
inferredcites →https://doi.org/10.5555/3199700.3199842openalex-snapshot
Generating FPGA-based image processing accelerators with Hipacc
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware Acceleration of Microwave Imaging Algorithms
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FPGA-Enabled Efficient Framework for High-Performance Intrusion Prevention Systems
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Modern High-Level Synthesis: Improving Productivity with a Multi-level Approach
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An Approach to Deploying Convolutional Neural Networks Based on FPGA Technology for Image Recognition
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Seamless FPGA Integration with Stream Processing Engines
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Learning Based Presilicon Estimation of Design Area from Early EDA Metrics
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Two-Stage Hierarchy-Aware Learning with Gradient Conflict Mitigation for HLS Latency and Resource Prediction
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Sequential Equivalence Checking for Specialized IR via Instrumentation-Based Symbolic Execution
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Accelerating Elliptic Curve Digital Signature Verification on FPGA for Secure Communication
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Real-Time FPGA-Accelerated Video Compression Using DCNv2-RNN Framework for High-Resolution and High-Frame-Rate Applications
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Data repair accelerating scheme for erasure-coded storage system based on FPGA and hierarchical parallel decoding structure
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Topology analysis and evolution trend prediction of secure propagation networks for short videos based on digital twin model
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Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA
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Deep Learning Accelerator Design for Lens Flare Attenuation using High-Level Synthesis
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Enhancing Laryngeal Spinocellular Carcinoma Image Security with DCT
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Neural Networks Implementations on FPGA for Biomedical Applications: A Review
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Artificial intelligence–driven high-level synthesis and behavioral simulation in very-large-scale integration (VLSI) design
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Hardware acceleration of complex HEP algorithms with HLS and FPGAs: Methodology and preliminary implementation
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Dynamic contention-aware workflow scheduling on shared bus-based CPU-FPGA heterogeneous computing systems
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High-level synthesis acceleration for an FPGA implementation of an optimized automatic target detection and classification algorithm for hyperspectral image analysis with Intel oneAPI
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Recent advances on reliability of FPGAs in a radiation environment
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A novel machine learning-driven optimization methodology for faster and more efficient design space exploration in high-level synthesis
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Spiking neural networks on FPGA: A survey of methodologies and recent advancements
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Reconfigurable acceleration for database systems: Taxonomy, techniques, and research challenges
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Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain
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A systematic review of machine learning-driven design space exploration in high-level synthesis
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A heuristic approach for near Pareto-optimal design space exploration in Approximate High-Level Synthesis
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High Level Synthesis in the Agentic Era
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Towards the transformation of MATLAB models into FPGA-Based hardware accelerators
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Exploring machine learning to hardware implementations for large data rate x-ray instrumentation
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rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA
inferred← citeshttps://doi.org/10.1109/access.2023.3303840openalex-snapshot
A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/access.2024.3491102openalex-snapshot
Research and Application of Signal Acquisition Algorithm for Beidou Navigation System
inferred← citeshttps://doi.org/10.1109/access.2024.3509606openalex-snapshot
Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration
inferred← citeshttps://doi.org/10.1109/access.2025.3540320openalex-snapshot
High-Level Synthesis for FPGAs—A Hardware Engineer’s Perspective
inferred← citeshttps://doi.org/10.1109/access.2025.3544515openalex-snapshot
A Survey on Real-Time Object Detection on FPGAs
inferred← citeshttps://doi.org/10.1109/access.2025.3570024openalex-snapshot
High-Performance Number Theoretic Transform on GPU Through radix2-CT and 4-Step Algorithms
inferred← citeshttps://doi.org/10.1109/access.2025.3602232openalex-snapshot
Automated Hardware Design Methodology for Digital Filters With High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/acit65614.2025.11185710openalex-snapshot
Generative AI-Assisted High-Level Design of Computer Devices: First Experience
inferred← citeshttps://doi.org/10.1109/asap57973.2023.00037openalex-snapshot
FarSlayer: Turnkey Acceleration of Legacy Software on Commodity FPGA Cards
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420379openalex-snapshot
H 2 NoC: A Hybrid NoC Architecture for FPGAs with Hardened Interconnects
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420433openalex-snapshot
Automatic Recursion Elimination using Recurrence Relations for Synthesis of Stack-free Hardware
inferred← citeshttps://doi.org/10.1109/ats59501.2023.10318028openalex-snapshot
A Survey on Fault-Tolerance Methods for SRAM-Based FPGAs in Radiation Environments
inferred← citeshttps://doi.org/10.1109/cgo68049.2026.11394843openalex-snapshot
Pyls: Enabling Python Hardware Synthesis with Dynamic Polymorphism via LCRS Encoding
inferred← citeshttps://doi.org/10.1109/coins65080.2025.11125726openalex-snapshot
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247686openalex-snapshot
An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133015openalex-snapshot
Optimizing Recovery Logic in Speculative High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/eeiss62553.2024.00011openalex-snapshot
Design and Implementation of System Communication Computing Acceleration Algorithm under Cloud Edge Collaboration
inferred← citeshttps://doi.org/10.1109/fccm62733.2025.00047openalex-snapshot
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
inferred← citeshttps://doi.org/10.1109/fccm62733.2025.00062openalex-snapshot
NoH: NoC Compilation in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00060openalex-snapshot
LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00079openalex-snapshot
Reconfigurable Computing Challenge: RapidScan High-Throughput Parameterized HLS-based Streaming String Matching Library for FPGAs
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00024openalex-snapshot
Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00025openalex-snapshot
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/gcce65946.2025.11274711openalex-snapshot
Hardware Implementation on MobileNetV2 for Multispectral Farmland Classification
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00034openalex-snapshot
Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408544openalex-snapshot
DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323754openalex-snapshot
AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323853openalex-snapshot
Robust GNN-Based Representation Learning for HLS
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240905openalex-snapshot
Augmented Co-Simulation for Fast Functional and System-Level Verification of HLS Accelerators
inferred← citeshttps://doi.org/10.1109/icccn65249.2025.11133817openalex-snapshot
Enabling Symbolic Execution for Hardware TCP/IP Stack based on AMD Vitis HLS
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00089openalex-snapshot
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
inferred← citeshttps://doi.org/10.1109/iccd63220.2024.00072openalex-snapshot
HEncode: A Highly Modularized and Efficient FPGA QC-LDPC Encoder using High Level Synthesis
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00088openalex-snapshot
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113451openalex-snapshot
An MLIR-Based Compiler for Hardware Acceleration with Recursion Support: (PhD Forum Paper)
inferred← citeshttps://doi.org/10.1109/iclad65226.2025.00038openalex-snapshot
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
inferred← citeshttps://doi.org/10.1109/icpeca60615.2024.10471036openalex-snapshot
Low-Power Design of Advanced Image Processing Algorithms under FPGA in Real-Time Applications
inferred← citeshttps://doi.org/10.1109/icramet62801.2024.10809195openalex-snapshot
High-Level Synthesis of FPGA-Based Chirp Match Filtering for Synthetic Aperture Radar Systems
inferred← citeshttps://doi.org/10.1109/icrera59003.2023.10269418openalex-snapshot
FPGA-Based FDNE Models for the Accurate Real-Time Simulation of Power Systems in Aircrafts
inferred← citeshttps://doi.org/10.1109/icsmacs68968.2026.11628653openalex-snapshot
The Multi-Modulation Orchestrator (MMO): Enabling Native Wi-Fi and IoT Convergence through Heterogeneous PHY Orchestration
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10181987openalex-snapshot
CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11044149openalex-snapshot
HLS Learning Approach: Efficient Optimization with Instruction Block Diagram
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11561911openalex-snapshot
An End-to-End Compilation Flow with Reinforcement Learning-Guided Logic Synthesis
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562269openalex-snapshot
Performance Pragma-Based Design Space Pruning and Exploration for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iseda62518.2024.10618013openalex-snapshot
Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528738openalex-snapshot
AutoAnnotate: Reinforcement Learning based Code Annotation for High Level Synthesis
inferred← citeshttps://doi.org/10.1109/jlt.2026.3728173openalex-snapshot
Algorithm-Hardware Co-Design for Bandwidth-Efficient DBA in Next-Generation PONs
inferred← citeshttps://doi.org/10.1109/jssc.2024.3522355openalex-snapshot
A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration
inferred← citeshttps://doi.org/10.1109/jstars.2024.3400883openalex-snapshot
Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA
inferred← citeshttps://doi.org/10.1109/lad62341.2024.10691860openalex-snapshot
An Iteratively-refined Dataset for High-Level Synthesis Functional Verification through LLM-Aided Bug Injection
inferred← citeshttps://doi.org/10.1109/lascas56464.2023.10108151openalex-snapshot
Exploring Multi-Parameter Optimization of Automated HLS Tools and the Difficulty of Setting Complex Constraints
inferred← citeshttps://doi.org/10.1109/les.2024.3446797openalex-snapshot
Enhancing HLS Performance Prediction on FPGAs Through Multimodal Representation Learning
inferred← citeshttps://doi.org/10.1109/mc.2024.3378380openalex-snapshot
The Role of Field-Programmable Gate Arrays in the Acceleration of Modern High-Performance Computing Workloads
inferred← citeshttps://doi.org/10.1109/mcas.2023.3325498openalex-snapshot
Women in Circuits and Systems (WiCAS) at NEWCAS 2023 [Women in CAS]
inferred← citeshttps://doi.org/10.1109/mcas.2023.3331327openalex-snapshot
An Interview With Professor Jason Cong [Interview]
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00040openalex-snapshot
A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs
inferred← citeshttps://doi.org/10.1109/mlcad62225.2024.10740257openalex-snapshot
Learning to Compare Hardware Designs for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/newcas58973.2024.10666303openalex-snapshot
CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign
inferred← citeshttps://doi.org/10.1109/ojcoms.2026.3665311openalex-snapshot
Low-Complexity and Low-Energy RNN-Enhanced Kalman Filter for Channel Estimation: A Case Study
inferred← citeshttps://doi.org/10.1109/sbesc60926.2023.10324241openalex-snapshot
GRASP-based High-Level Synthesis Design Space Exploration for FPGAs
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00148openalex-snapshot
Acceleration of Graph Neural Networks with Heterogenous Accelerators Architecture
inferred← citeshttps://doi.org/10.1109/socc66126.2025.11235352openalex-snapshot
Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper
inferred← citeshttps://doi.org/10.1109/tc.2022.3213177openalex-snapshot
ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design
inferred← citeshttps://doi.org/10.1109/tcasai.2024.3485522openalex-snapshot
Harnessing GNNs for Robust Representation Learning in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcsi.2026.3660017openalex-snapshot
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3353690openalex-snapshot
FPGA-Accelerated Sim-to-Real Control Policy Learning for Robotic Arms
inferred← citeshttps://doi.org/10.1145/3524108openalex-snapshot
Democratizing Domain-Specific Computing
inferred← citeshttps://doi.org/10.1145/3543622.3573210openalex-snapshot
CHARM: C omposing H eterogeneous A ccele R ators for M atrix Multiply on Versal ACAP Architecture
inferred← citeshttps://doi.org/10.1145/3581757openalex-snapshot
HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL
inferred← citeshttps://doi.org/10.1145/3587135.3592766openalex-snapshot
Exploration of Synthesis Methods from Simulink Models to FPGA for Aerospace Applications
inferred← citeshttps://doi.org/10.1145/3593025openalex-snapshot
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration
inferred← citeshttps://doi.org/10.1145/3599972openalex-snapshot
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining
inferred← citeshttps://doi.org/10.1145/3607888openalex-snapshot
Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis
inferred← citeshttps://doi.org/10.1145/3607888.3608962openalex-snapshot
Special Session: Machine Learning for Embedded System Design
inferred← citeshttps://doi.org/10.1145/3626103openalex-snapshot
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow
inferred← citeshttps://doi.org/10.1145/3629523openalex-snapshot
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler
inferred← citeshttps://doi.org/10.1145/3637543.3652979openalex-snapshot
A DNN-based Background Segmentation Accelerator for FPGA-equipped satellites
inferred← citeshttps://doi.org/10.1145/3649329.3655945openalex-snapshot
High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3649329.3663517openalex-snapshot
Invited: New Solutions on LLM Acceleration, Optimization, and Application
inferred← citeshttps://doi.org/10.1145/3650729openalex-snapshot
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems
inferred← citeshttps://doi.org/10.1145/3656401openalex-snapshot
Allo: A Programming Model for Composable Accelerator Design
inferred← citeshttps://doi.org/10.1145/3658617.3697621openalex-snapshot
OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLM
inferred← citeshttps://doi.org/10.1145/3658617.3697719openalex-snapshot
Hardware Synthesizable Exceptions using Continuations
inferred← citeshttps://doi.org/10.1145/3658617.3697757openalex-snapshot
Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
inferred← citeshttps://doi.org/10.1145/3670474.3685940openalex-snapshot
Learning to Compare Hardware Designs for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3676536.3676649openalex-snapshot
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
inferred← citeshttps://doi.org/10.1145/3676849openalex-snapshot
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
inferred← citeshttps://doi.org/10.1145/3677035openalex-snapshot
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators
inferred← citeshttps://doi.org/10.1145/3686163openalex-snapshot
CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture
inferred← citeshttps://doi.org/10.1145/3690389openalex-snapshot
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition
inferred← citeshttps://doi.org/10.1145/3704413.3764472openalex-snapshot
FlexRFML: Dynamic Neural Networks on FPGAs for Next-Generation Radio Spectrum Perception
inferred← citeshttps://doi.org/10.1145/3705325openalex-snapshot
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design
inferred← citeshttps://doi.org/10.1145/3706628.3708828openalex-snapshot
InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs
inferred← citeshttps://doi.org/10.1145/3706628.3708866openalex-snapshot
Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration
inferred← citeshttps://doi.org/10.1145/3706628.3708869openalex-snapshot
SAT-Accel: A Modern SAT Solver on a FPGA
inferred← citeshttps://doi.org/10.1145/3706628.3708873openalex-snapshot
A Unified Framework for Automated Code Transformation and Pragma Insertion
inferred← citeshttps://doi.org/10.1145/3706628.3708878openalex-snapshot
Stream-HLS: Towards Automatic Dataflow Acceleration
inferred← citeshttps://doi.org/10.1145/3718737openalex-snapshot
Toward Understanding FPGA Synthesis Tool Bugs
inferred← citeshttps://doi.org/10.1145/3719276.3727949openalex-snapshot
POSTER: A System-level HW/SW Co-simulation Framework for HLS-generated Accelerators
inferred← citeshttps://doi.org/10.1145/3721289openalex-snapshot
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning
inferred← citeshttps://doi.org/10.1145/3723046openalex-snapshot
Productively Generating a High-Performance Linear Algebra Library on FPGAs
inferred← citeshttps://doi.org/10.1145/3725783.3764402openalex-snapshot
FPGAs Are the Hero In-Network Computing Needs
inferred← citeshttps://doi.org/10.1145/3764664openalex-snapshot
A Taxonomy of the High-Level Synthesis Ecosystem for Heterogeneous FPGA Systems
inferred← citeshttps://doi.org/10.1145/3771581openalex-snapshot
µ-VF: Enabling Virtualization of Embedded FPGAs
inferred← citeshttps://doi.org/10.1145/3787491openalex-snapshot
High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing
inferred← citeshttps://doi.org/10.1145/3795509openalex-snapshot
Detecting Hardware Trojans in High-Level Synthesis-Generated RTL using Large Language Models
inferred← citeshttps://doi.org/10.1145/3831666openalex-snapshot
A Quarter of a Century of Neuromorphic Architectures on FPGAs - An Overview
inferred← citeshttps://doi.org/10.1177/17545730241297786openalex-snapshot
Advanced Security Strategies for Software Vulnerability Protection: A Multi-Scale Detection Model With FPGA-RFID
inferred← citeshttps://doi.org/10.12792/iciae2023.039openalex-snapshot
Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language
inferred← citeshttps://doi.org/10.1561/1000000063-3openalex-snapshot
Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis
inferred← citeshttps://doi.org/10.1609/aaai.v39i17.34033openalex-snapshot
Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis
inferred← citeshttps://doi.org/10.1631/fitee.2300720openalex-snapshot
Quant 4.0: engineering quantitative investment with automated, explainable, and knowledge-driven artificial intelligence
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3511152/v1openalex-snapshot
FPGA-Based Image Denoising Using Adaptive Vector Directional Distance Filter: Performance Analysis and Comparison
inferred← citeshttps://doi.org/10.2139/ssrn.5269733openalex-snapshot
High-Level Synthesis Acceleration for an Fpga Implementation of an Optimized Automatic Target Detection and Classification Algorithm for Hyperspectral Image Analysis with Intel Oneapi
inferred← citeshttps://doi.org/10.2139/ssrn.5388098openalex-snapshot
An Input-Aware Heuristic with High-Level Synthesis of Approximate Hardware
inferred← citeshttps://doi.org/10.2139/ssrn.6216536openalex-snapshot
Direct Modification of FPGA Bitstream Under Physical Resource-Configuration Frame Mapping: From Model Construction to Functional Verification
inferred← citeshttps://doi.org/10.2139/ssrn.6642163openalex-snapshot
Direct Modification of FPGA Bitstream Under Physical Resource-Configuration Frame Mapping: From Model Construction to Functional Verification
inferred← citeshttps://doi.org/10.23919/date56975.2023.10136921openalex-snapshot
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem
inferred← citeshttps://doi.org/10.23919/date64628.2025.10993042openalex-snapshot
Operation Dependency Graph-Based Scheduling for High-Level Synthesis
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539716openalex-snapshot
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
inferred← citeshttps://doi.org/10.23919/edhpc59100.2023.10396136openalex-snapshot
High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline Model
inferred← citeshttps://doi.org/10.32657/10356/172513openalex-snapshot
Accelerating sparse matrix operations on FPGAs with on/off-chip memories
inferred← citeshttps://doi.org/10.3389/fhpcp.2025.1572844openalex-snapshot
FPGA innovation research in the Netherlands: present landscape and future outlook
inferred← citeshttps://doi.org/10.3390/computers14050189openalex-snapshot
AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow
inferred← citeshttps://doi.org/10.3390/computers15080498openalex-snapshot
A Memory-Centric SoC-FPGA Framework for Incremental 2D Delaunay Triangulation
inferred← citeshttps://doi.org/10.3390/cryptography9010020openalex-snapshot
BPAP: FPGA Design of a RISC-like Processor for Elliptic Curve Cryptography Using Task-Level Parallel Programming in High-Level Synthesis
inferred← citeshttps://doi.org/10.3390/electronics13010234openalex-snapshot
High-Throughput MPSoC Implementation of Sparse Bayesian Learning Algorithm
inferred← citeshttps://doi.org/10.3390/electronics15122603openalex-snapshot
Optimizing Convolutional Operation and Dataflow in FPGA Acceleration of Bayesian Convolutional Neural Network
inferred← citeshttps://doi.org/10.3390/mi14112030openalex-snapshot
Optimizing the Performance of the Sparse Matrix–Vector Multiplication Kernel in FPGA Guided by the Roofline Model
inferred← citeshttps://doi.org/10.47749/t/unicamp.2024.1436248openalex-snapshot
Dynamic network slicing for user mobility support in 5G networks
inferred← citeshttps://doi.org/10.48084/etasr.7081openalex-snapshot
Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA
inferred← citeshttps://doi.org/10.5753/sbc.13058.5.4openalex-snapshot
Desafios para a Computação Energeticamente Eficiente
inferred← citeshttps://doi.org/10.70675/54aa2f4ez3f0cz4040zac42z67d0d0297b16openalex-snapshot
Multi-parameter Joint Estimation Method and Implementation of Sparse Underwater Acoustic Signals
inferred← citeshttps://doi.org/10.70675/7954fab8ze891z46eeza55az2fc9177718dcopenalex-snapshot
Design space exploration of image processing algorithms on FPGAs
inferred← citeshttps://doi.org/10.70675/9b86665cz79bbz400fz9d0bz69433c967981openalex-snapshot
Efficient CNN inference acceleration on FPGAs : a pattern pruning-driven approach
inferred← citeshttps://doi.org/10.70675/f66d4d56z7efaz4c3dz968dz4dcae7036781openalex-snapshot
Using HLS to raise the design abstraction level for faster exploration of different CPU Micro-architectures
inferred← citeshttps://doi.org/10.7240/jeps.1864699openalex-snapshot
Comparative Analysis of HLS- and RTL-Based SHA-256 Accelerators on a Zynq FPGA: Performance, Power, and Resource Utilization
inferred← citeshttps://doi.org/10.7240/jeps.1888024openalex-snapshot
Comparative Analysis of Different Performances in Digital Music Recordings Using Information Theory Metrics and Audio Features
inferred← citeshttps://doi.org/10.7287/peerj-cs.1166v0.1/reviews/1openalex-snapshot
Peer Review #1 of "A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities (v0.1)"
inferred← citeshttps://doi.org/10.7287/peerj-cs.1166v0.1/reviews/2openalex-snapshot
Peer Review #2 of "A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities (v0.1)"
inferred← citeshttps://doi.org/10.7287/peerj-cs.1166v0.2/reviews/1openalex-snapshot
Peer Review #1 of "A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities (v0.2)"
inferred← citeshttps://doi.org/10.7287/peerj-cs.1166v0.2/reviews/2openalex-snapshot
Peer Review #2 of "A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities (v0.2)"
inferred← citeshttps://doi.org/10.7717/peerj-cs.1166openalex-snapshot
A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.