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Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays

https://doi.org/10.1007/bf00924526
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-17943-7_135openalex-snapshot
Systolic array synthesis by static analysis of program dependencies
inferredcites →https://doi.org/10.1007/3-540-18991-2_42openalex-snapshot
A Wavefront Array Processor using dataflow processing elements
inferredcites →https://doi.org/10.1007/978-1-4613-1077-8openalex-snapshot
Parallel Programming and Compilers
inferredcites →https://doi.org/10.1007/978-3-642-62035-5openalex-snapshot
An Introduction to the Geometry of Numbers
inferredcites →https://doi.org/10.1007/978-3-662-25209-3_17openalex-snapshot
Affine Timings for Systems of Affine Recurrence Equations
inferredcites →https://doi.org/10.1007/bf00925828openalex-snapshot
The ALPHA language and its use for the design of systolic arrays
inferredcites →https://doi.org/10.1007/bf00930616openalex-snapshot
Calculus of space-optimal mappings of systolic algorithms on processor arrays
inferredcites →https://doi.org/10.1007/bf01192158openalex-snapshot
Geometrical tools to map systems of affine recurrence equations on regular arrays
inferredcites →https://doi.org/10.1007/bf01379404openalex-snapshot
Some efficient solutions to the affine scheduling problem. Part II. Multidimensional time
inferredcites →https://doi.org/10.1007/bf01407835openalex-snapshot
Some efficient solutions to the affine scheduling problem. I. One-dimensional time
inferredcites →https://doi.org/10.1007/bf01558666openalex-snapshot
Synthesizing systolic arrays with control signals from recurrence equations
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bfb0040399openalex-snapshot
Converting affine recurrence equations to quasi-uniform recurrence equations
inferredcites →https://doi.org/10.1016/0304-3975(85)90091-xopenalex-snapshot
Topological transformations as a tool in the design of systolic networks
inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot
Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1057/jors.1987.94openalex-snapshot
Theory of Linear and Integer Programming
inferredcites →https://doi.org/10.1109/12.123393openalex-snapshot
Optimization of computation time for systolic arrays
inferredcites →https://doi.org/10.1109/12.90251openalex-snapshot
Time optimal linear schedules for algorithms with uniform dependencies
inferredcites →https://doi.org/10.1109/12.9735openalex-snapshot
Synthesizing linear array algorithms from nested FOR loop algorithms
inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot
Regular iterative algorithms and their implementation on processor arrays
inferredcites →https://doi.org/10.1109/71.265946openalex-snapshot
On loop transformations for generalized cycle shrinking
inferredcites →https://doi.org/10.1109/arrays.1988.18077openalex-snapshot
Scheduling a system of affine recurrence equations onto a systolic array
inferredcites →https://doi.org/10.1109/asap.1990.145495openalex-snapshot
A design methodology for fixed-size systolic arrays
inferredcites →https://doi.org/10.1109/asap.1991.238908openalex-snapshot
Synthesizing systolic arrays: some recent developments
inferredcites →https://doi.org/10.1109/asap.1992.218583openalex-snapshot
Linear scheduling is close to optimality
inferredcites →https://doi.org/10.1109/icassp.1985.1168513openalex-snapshot
Systematic approaches to the design of algorithmically specified systolic arrays
inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot
VLSI Array processors
inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot
Why systolic architectures?
inferredcites →https://doi.org/10.1109/tc.1982.1675929openalex-snapshot
On the Analysis and Synthesis of VLSI Algorithms
inferredcites →https://doi.org/10.1109/tc.1985.1676516openalex-snapshot
The Design of Optimal Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1109/tcad.1987.1270243openalex-snapshot
ADVIS: A Software Package for the Design of Systolic Arrays
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/360827.360844openalex-snapshot
The parallel execution of DO loops
inferredcites →https://doi.org/10.2307/253980openalex-snapshot
Theory of Linear and Integer Programming

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/047134608x.w7220openalex-snapshot
Vlsi Signal Processing
inferred← citeshttps://doi.org/10.1016/b978-012170960-0/50067-0openalex-snapshot
VLSI Signal Processing
inferred← citeshttps://doi.org/10.1016/s0010-4655(01)00231-4openalex-snapshot
Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming
inferred← citeshttps://doi.org/10.1016/s0010-4655(01)00234-xopenalex-snapshot
Automatic implementation of affine iterative algorithms: Design flow and communication synthesis
inferred← citeshttps://doi.org/10.1023/a:1007944932429openalex-snapshot
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP
inferred← citeshttps://doi.org/10.1023/a:1007963228049openalex-snapshot
Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming
inferred← citeshttps://doi.org/10.1023/a:1008008231304openalex-snapshot
On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming
inferred← citeshttps://doi.org/10.1023/a:1008012332212openalex-snapshot
A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures
inferred← citeshttps://doi.org/10.1023/a:1008082726678openalex-snapshot
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation
inferred← citeshttps://doi.org/10.1023/b:vlsi.0000003027.47559.1eopenalex-snapshot
A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins
inferred← citeshttps://doi.org/10.1109/32.842951openalex-snapshot
Automatic mapping of system of N-dimensional affine recurrence equations (SARE) onto distributed memory parallel systems
inferred← citeshttps://doi.org/10.1109/43.748156openalex-snapshot
Processor array design with FPGA area constraint
inferred← citeshttps://doi.org/10.1109/ispan.1997.645125openalex-snapshot
An operation placement and scheduling scheme for cache and communication localities in fine-grain parallel architectures
inferred← citeshttps://doi.org/10.1145/582034.582063openalex-snapshot
Parallel dedicated hardware devices for heterogeneous computations
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