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Synthesizing systolic arrays with control signals from recurrence equations

https://doi.org/10.1007/bf01558666
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-17179-7_30openalex-snapshot
On synthesizing systolic arrays from Recurrence Equations with Linear Dependencies
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Systolic array synthesis by static analysis of program dependencies
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An Introduction to the Geometry of Numbers
inferredcites →https://doi.org/10.1007/bf00282618openalex-snapshot
The derivation of systolic implementations of programs
inferredcites →https://doi.org/10.1007/bf01558666openalex-snapshot
Synthesizing systolic arrays with control signals from recurrence equations
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
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Converting affine recurrence equations to quasi-uniform recurrence equations
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Synthesizing systolic arrays from recurrence equations
inferredcites →https://doi.org/10.1016/0743-7315(86)90010-9openalex-snapshot
A design methodology for synthesizing parallel algorithms and architectures
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Regular iterative algorithms and their implementation on processor arrays
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Scheduling a system of affine recurrence equations onto a systolic array
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Why systolic architectures?
inferredcites →https://doi.org/10.1109/mc.1985.1662798openalex-snapshot
A Transformational Model of VLSI Systolic Design
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On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/proc.1987.13882openalex-snapshot
Array architectures for iterative algorithms
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Optimizing synchronous systems
inferredcites →https://doi.org/10.1109/tc.1985.1676516openalex-snapshot
The Design of Optimal Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676744openalex-snapshot
Mapping Homogeneous Graphs on Linear Arrays
inferredcites →https://doi.org/10.1117/12.944011openalex-snapshot
Selecting Systolic Designs Using Linear Transformations Of Space-Time
inferredcites →https://doi.org/10.1117/12.960497openalex-snapshot
What is a Systolic Algorithm?
inferredcites →https://doi.org/10.1137/0213034openalex-snapshot
A Mathematical Model for the Verification of Systolic Networks
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/321992.321996openalex-snapshot
A Transformation System for Developing Recursive Programs
inferredcites →https://doi.org/10.1145/512644.512656openalex-snapshot
A parallel language and its compilation to multiprocessor machines or VLSI
inferredcites →https://doi.org/10.1145/773453.808186openalex-snapshot
Data broadcasting in linearly scheduled array processors
inferredcites →https://doi.org/10.1145/800015.808186openalex-snapshot
Data broadcasting in linearly scheduled array processors
inferredcites →https://doi.org/10.7907/96kfn-x5548openalex-snapshot
Space-Time Algorithms: Semantics and Methodology

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Systematic approach and software tool for systolic design
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Affine Permutations of Matrices on Mesh-Connected Arrays
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GPU Accelerated RNA Folding Algorithm
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Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays
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A systolic array for pyramidal algorithms
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Systematic generation of linear allocation functions in systolic array design
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Preconditioning index set transformations for time-optimal affine scheduling
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Systolic partitioning algorithms
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Synthesis of systolic algorithm design
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Synthesizing systolic arrays from recurrence equations
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Automating the design of systolic arrays
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An improved systolic algorithm for the algebraic path problem
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Computability of recurrence equations
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Synthesis of time-optimal systolic arrays with cells with inner structure
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GPU Accelerated RNA Folding Algorithm
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Derivation of systolic algorithms for the algebraic path problem by recurrence transformations
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Synthesis aspects in the design of efficient processor arrays from affine recurrence equations
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Vlsi Array Architectures for Pyramid Vector Quantization
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