On the public citation graph
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.compeleceng.2012.09.013openalex-snapshot
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption
inferredcites →https://doi.org/10.1016/j.sysarc.2012.10.004openalex-snapshot
A survey on application mapping strategies for Network-on-Chip design
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/date.2005.91openalex-snapshot
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles
inferredcites →https://doi.org/10.1109/dsd.2006.81openalex-snapshot
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
inferredcites →https://doi.org/10.1109/iccd.2008.4751856openalex-snapshot
Contention-aware application mapping for Network-on-Chip communication architectures
inferredcites →https://doi.org/10.1109/iccd.2012.6378665openalex-snapshot
CoNA: Dynamic application mapping for congestion reduction in many-core systems
inferredcites →https://doi.org/10.1109/issoc.2005.1595649openalex-snapshot
Run-time Mapping of Applications to a Heterogeneous SoC
inferredcites →https://doi.org/10.1109/issoc.2008.4694878openalex-snapshot
Congestion-aware task mapping in heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/itng.2009.239openalex-snapshot
Traffic Aware Scheduling Algorithm for Network on Chip
inferredcites →https://doi.org/10.1109/tvlsi.2013.2278334openalex-snapshot
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip
inferredcites →https://doi.org/10.1145/1084834.1084856openalex-snapshot
Key research problems in NoC design
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1120725.1120738openalex-snapshot
Time and energy efficient mapping of embedded applications onto NoCs
inferredcites →https://doi.org/10.1145/1531542.1531638openalex-snapshot
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices
inferredcites →https://doi.org/10.1145/2463209.2488782openalex-snapshot
Smart hill climbing for agile dynamic mapping in many-core systems
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/996566.996637openalex-snapshot
Operating-system controlled network on chip
inferredcites →https://doi.org/10.4018/978-1-61520-807-4.ch001openalex-snapshot
A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems
inferredcites →https://doi.org/10.5555/1266366.1266572openalex-snapshot
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
inferredcites →https://doi.org/10.5555/2492708.2493089openalex-snapshot
Congestion-aware scheduling for NoC-based reconfigurable systems
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-023-05424-8openalex-snapshot
A hot-module-aware mapping approach in network-on-chip
inferred← citeshttps://doi.org/10.1007/s41870-023-01542-xopenalex-snapshot
Contention-free dynamic task scheduling approach for network-on-chip based quad-core systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.08.002openalex-snapshot
Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102020openalex-snapshot
Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems
inferred← citeshttps://doi.org/10.1109/access.2020.2982675openalex-snapshot
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
inferred← citeshttps://doi.org/10.1109/access.2023.3329233openalex-snapshot
A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms
inferred← citeshttps://doi.org/10.1145/3055512openalex-snapshot
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3177652/v1openalex-snapshot
Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey
inferred← citeshttps://doi.org/10.21553/rev-jec.147openalex-snapshot
A Survey on Reconfigurable System-on-Chips
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474079openalex-snapshot
A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing
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