On the public citation graph
Adaptive Cache Management for Energy-Efficient GPU Computing
0 signed · 185 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2012.6168947openalex-snapshot
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
inferredcites →https://doi.org/10.1109/hpca.2013.6522351openalex-snapshot
Cache coherence for GPU architectures
inferredcites →https://doi.org/10.1109/hpca.2014.6835930openalex-snapshot
QuickRelease: A throughput-oriented approach to release consistency on GPUs
inferredcites →https://doi.org/10.1109/hpca.2014.6835938openalex-snapshot
MRPB: Memory request prioritization for massively parallel processors
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferredcites →https://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferredcites →https://doi.org/10.1109/micro.2010.39openalex-snapshot
Memory Latency Reduction via Thread Throttling
inferredcites →https://doi.org/10.1109/micro.2012.16openalex-snapshot
Cache-Conscious Wavefront Scheduling
inferredcites →https://doi.org/10.1109/micro.2012.18openalex-snapshot
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
inferredcites →https://doi.org/10.1109/micro.2012.43openalex-snapshot
Improving Cache Management Policies Using Dynamic Reuse Distances
inferredcites →https://doi.org/10.1109/mm.2014.4openalex-snapshot
Cache Coherence for GPU Architectures
inferredcites →https://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/2000064.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferredcites →https://doi.org/10.1145/2145816.2145820openalex-snapshot
Efficient performance evaluation of memory hierarchy for highly multithreaded graphics processors
inferredcites →https://doi.org/10.1145/2155620.2155656openalex-snapshot
Improving GPU performance via large warps and two-level warp scheduling
inferredcites →https://doi.org/10.1145/2159430.2159443openalex-snapshot
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs
inferredcites →https://doi.org/10.1145/2304576.2304582openalex-snapshot
Characterizing and improving the use of demand-fetched caches in GPUs
inferredcites →https://doi.org/10.1145/2540708.2540717openalex-snapshot
A locality-aware memory hierarchy for energy-efficient GPU architectures
inferredcites →https://doi.org/10.1145/2540708.2540718openalex-snapshot
Divergence-aware warp scheduling
inferredcites →https://doi.org/10.1145/2540708.2540742openalex-snapshot
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads
inferredcites →https://doi.org/10.1145/2613908.2613909openalex-snapshot
Adaptive Cache Bypass and Insertion for Many-core Accelerators
inferredcites →https://doi.org/10.1145/264107.264213openalex-snapshot
Run-time adaptive cache hierarchy management via reference analysis
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.2139/ssrn.4522820openalex-extracted
Design of Shared Storage Based on Cache Decouple
inferred← citeshttps://doi.org/10.1002/cpe.4104openalex-snapshot
Incorporating selective victim cache into GPGPU for high‐performance computing
inferred← citeshttps://doi.org/10.1002/cpe.5438openalex-snapshot
Efficient content retrieval in fog zone using Nano‐Caches
inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_16openalex-snapshot
A Quantitative Study of Locality in GPU Caches
inferred← citeshttps://doi.org/10.1007/978-3-031-01759-9openalex-snapshot
General-Purpose Graphics Processor Architectures
inferred← citeshttps://doi.org/10.1007/978-3-031-64608-9_1openalex-snapshot
e-CLAS: Effective GPUDirect I/O Classification Scheme
inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_17openalex-snapshot
Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units
inferred← citeshttps://doi.org/10.1007/s00607-016-0537-2openalex-snapshot
LU factorization on heterogeneous systems: an energy-efficient approach towards high performance
inferred← citeshttps://doi.org/10.1007/s10586-017-1396-0openalex-snapshot
Memory-aware TLP throttling and cache bypassing for GPUs
inferred← citeshttps://doi.org/10.1007/s10766-022-00729-2openalex-snapshot
A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads
inferred← citeshttps://doi.org/10.1007/s11227-018-2389-3openalex-snapshot
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures
inferred← citeshttps://doi.org/10.1007/s11227-022-04621-1openalex-snapshot
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads
inferred← citeshttps://doi.org/10.1007/s11227-022-04657-3openalex-snapshot
Criticality-aware priority to accelerate GPU memory access
inferred← citeshttps://doi.org/10.1007/s11227-022-04878-6openalex-snapshot
Aggressive GPU cache bypassing with monolithic 3D-based NoC
inferred← citeshttps://doi.org/10.1007/s11227-023-05787-yopenalex-snapshot
GPU thread throttling for page-level thrashing reduction via static analysis
inferred← citeshttps://doi.org/10.1016/b978-0-12-803738-6.00020-3openalex-snapshot
Architecting the last-level cache for GPUs using STT-MRAM nonvolatile memory
inferred← citeshttps://doi.org/10.1016/j.future.2017.02.036openalex-snapshot
Locality based warp scheduling in GPGPUs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.09.001openalex-snapshot
Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.01.003openalex-snapshot
Quantifying the performance and energy efficiency of advanced cache indexing for GPGPU computing
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.09.007openalex-snapshot
Early miss prediction based periodic cache bypassing for high performance GPUs
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104301openalex-snapshot
Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures
inferred← citeshttps://doi.org/10.1016/j.parco.2026.103208openalex-snapshot
A comprehensive survey on multi-GPU systems
inferred← citeshttps://doi.org/10.1049/iet-cdt.2017.0004openalex-snapshot
Locality‐protected cache allocation scheme with low overhead on GPUs
inferred← citeshttps://doi.org/10.1049/iet-cdt.2019.0092openalex-snapshot
Survey on memory management techniques in heterogeneous computing systems
inferred← citeshttps://doi.org/10.1109/access.2018.2818193openalex-snapshot
DyCache: Dynamic Multi-Grain Cache Management for Irregular Memory Accesses on GPU
inferred← citeshttps://doi.org/10.1109/access.2018.2876201openalex-snapshot
Accelerating BFS via Data Structure-Aware Prefetching on GPU
inferred← citeshttps://doi.org/10.1109/aiccsa.2018.8612877openalex-snapshot
Evaluating Cache Power Dissipation Across Different Process Technologies
inferred← citeshttps://doi.org/10.1109/bdcloud.2018.00022openalex-snapshot
Tail-PASS: Resource-Based Cache Management for Tiled Graphics Rendering Hardware
inferred← citeshttps://doi.org/10.1109/cgo57630.2024.10444795openalex-snapshot
Energy-Aware Tile Size Selection for Affine Programs on GPUs
inferred← citeshttps://doi.org/10.1109/compsac57700.2023.00022openalex-snapshot
L2 Cache Access Pattern Analysis using Static Profiling of an Application
inferred← citeshttps://doi.org/10.1109/fccm.2018.00034openalex-snapshot
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms
inferred← citeshttps://doi.org/10.1109/hpca.2018.00027openalex-snapshot
Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls
inferred← citeshttps://doi.org/10.1109/hpca.2018.00042openalex-snapshot
G-TSC: Timestamp Based Coherence for GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2018.00048openalex-snapshot
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning
inferred← citeshttps://doi.org/10.1109/hpca.2019.00055openalex-snapshot
FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads
inferred← citeshttps://doi.org/10.1109/hpca.2019.00061openalex-snapshot
Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning
inferred← citeshttps://doi.org/10.1109/hpca.2019.00063openalex-snapshot
Understanding the Future of Energy Efficiency in Multi-Module GPUs
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00087openalex-snapshot
Guser: A GPGPU Power Stressmark Generator
inferred← citeshttps://doi.org/10.1109/hpcc64274.2024.00018openalex-snapshot
Pseudo-Cache: Extending the Access Scope of Requests with Global Perspective in GPUs
inferred← citeshttps://doi.org/10.1109/iccac.2017.17openalex-snapshot
Application-Specific Autonomic Cache Tuning for General Purpose GPUs
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203754openalex-snapshot
Exploring cache bypassing and partitioning for multi-tasking on GPUs
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753271openalex-snapshot
Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUs
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753308openalex-snapshot
IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
inferred← citeshttps://doi.org/10.1109/iccd.2017.111openalex-snapshot
BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads
inferred← citeshttps://doi.org/10.1109/iccd.2018.00061openalex-snapshot
BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement
inferred← citeshttps://doi.org/10.1109/icftic57696.2022.10075135openalex-snapshot
ACWS: Adaptive Cache-state Aware Warp Scheduling Based on Cache Feature Analysis
inferred← citeshttps://doi.org/10.1109/iciafs.2016.7946534openalex-snapshot
To use or not to use: CPUs' cache optimization techniques on GPGPUs
inferred← citeshttps://doi.org/10.1109/icisfall51598.2021.9627400openalex-snapshot
A Survey of GPGPU Parallel Processing Architecture Performance Optimization
inferred← citeshttps://doi.org/10.1109/icpads.2016.0122openalex-snapshot
Selectively GPU Cache Bypassing for Un-Coalesced Loads
inferred← citeshttps://doi.org/10.1109/icpads.2016.0130openalex-snapshot
An Energy-Efficient Implementation of LU Factorization on Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581276openalex-snapshot
ID-cache: instruction and memory divergence based cache management for GPUs
inferred← citeshttps://doi.org/10.1109/inocon60754.2024.10512116openalex-snapshot
A Survey of Caching Techniques for General Purpose Graphics Processing Units
inferred← citeshttps://doi.org/10.1109/ipdps.2016.89openalex-snapshot
X: A Comprehensive Analytic Model for Parallel Machines
inferred← citeshttps://doi.org/10.1109/ipdps.2017.106openalex-snapshot
Power Efficient Sharing-Aware GPU Data Management
inferred← citeshttps://doi.org/10.1109/ipdps.2017.81openalex-snapshot
Elastic-Cache: GPU Cache Architecture for Efficient Fine- and Coarse-Grained Cache-Line Management
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00025openalex-snapshot
CIAO: Cache Interference-Aware Throughput-Oriented Architecture and Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.11openalex-snapshot
High Performance Parallel Graph Coloring on GPGPUs
inferred← citeshttps://doi.org/10.1109/isca.2016.26openalex-snapshot
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs
inferred← citeshttps://doi.org/10.1109/isca.2016.59openalex-snapshot
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
inferred← citeshttps://doi.org/10.1109/isca.2018.00074openalex-snapshot
The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00052openalex-snapshot
FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining
inferred← citeshttps://doi.org/10.1109/islped65674.2025.11261765openalex-snapshot
Repurpose Accel-Sim for Next Generation NVIDIA Jetson GPU Architectural Design
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-sustaincom-socialcom48970.2019.00191openalex-snapshot
Architectural Implications in Graph Processing of Accelerator with Gardenia Benchmark Suite
inferred← citeshttps://doi.org/10.1109/lca.2026.3673140openalex-snapshot
LWAL: Lightweight Adaptive Learning-Driven Cache Bypassing for GPUs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783717openalex-snapshot
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00028openalex-snapshot
DTexL: Decoupled Raster Pipeline for Texture Locality
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00029openalex-snapshot
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00070openalex-snapshot
Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture
inferred← citeshttps://doi.org/10.1109/nas.2017.8026851openalex-snapshot
DD-L1D: Improving the Decoupled L1D Efficiency for GPU Architecture
inferred← citeshttps://doi.org/10.1109/pact.2015.38openalex-snapshot
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
inferred← citeshttps://doi.org/10.1109/pact.2015.60openalex-snapshot
Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00019openalex-snapshot
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
inferred← citeshttps://doi.org/10.1109/pccc.2016.7820638openalex-snapshot
A reuse distance based performance analysis on GPU L1 data cache
inferred← citeshttps://doi.org/10.1109/pdcat.2016.041openalex-snapshot
Accelerator-Centered Programming on Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/pdp2018.2018.00069openalex-snapshot
Studying Victim Caches in GPUs
inferred← citeshttps://doi.org/10.1109/tc.2017.2776272openalex-snapshot
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
inferred← citeshttps://doi.org/10.1109/tc.2019.2907591openalex-snapshot
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance
inferred← citeshttps://doi.org/10.1109/tc.2020.3026043openalex-snapshot
MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
inferred← citeshttps://doi.org/10.1109/tc.2025.3566898openalex-snapshot
Advanced Maximal Biclique Enumeration on GPUs Using Bitmaps
inferred← citeshttps://doi.org/10.1109/tcad.2015.2424962openalex-snapshot
An Efficient Compiler Framework for Cache Bypassing on GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2017.2681072openalex-snapshot
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2017.2764886openalex-snapshot
Optimizing Cache Bypassing and Warp Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2024.3443707openalex-snapshot
GPU Performance Optimization via Intergroup Cache Cooperation
inferred← citeshttps://doi.org/10.1109/tmc.2025.3599524openalex-snapshot
Towards Accurate Training Time Estimation for On-Device Heterogeneous Federated Learning
inferred← citeshttps://doi.org/10.1109/tpds.2016.2627560openalex-snapshot
SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme
inferred← citeshttps://doi.org/10.1109/tpds.2017.2773516openalex-snapshot
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
inferred← citeshttps://doi.org/10.1109/tpds.2018.2868658openalex-snapshot
Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache Management
inferred← citeshttps://doi.org/10.1109/tpds.2022.3154315openalex-snapshot
OSM: Off-Chip Shared Memory for GPUs
inferred← citeshttps://doi.org/10.1109/trustcom.2016.0237openalex-snapshot
Locality Protected Dynamic Cache Allocation Scheme on GPUs
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2584623openalex-snapshot
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU
inferred← citeshttps://doi.org/10.1145/2716282.2716291openalex-snapshot
Efficient utilization of GPGPU cache hierarchy
inferred← citeshttps://doi.org/10.1145/2751205.2751229openalex-snapshot
Leveraging Silicon-Photonic NoC for Designing Scalable GPUs
inferred← citeshttps://doi.org/10.1145/2751205.2751237openalex-snapshot
Locality-Driven Dynamic GPU Cache Bypassing
inferred← citeshttps://doi.org/10.1145/2768177.2768179openalex-snapshot
On the Feasibility of Advanced Cache Indexing for High-Performance and Energy-Efficient GPGPU Computing
inferred← citeshttps://doi.org/10.1145/2807591.2807606openalex-snapshot
Adaptive and transparent cache bypassing for GPUs
inferred← citeshttps://doi.org/10.1145/2830772.2830813openalex-snapshot
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs
inferred← citeshttps://doi.org/10.1145/2897937.2897966openalex-snapshot
A model-driven approach to warp/thread-block level GPU cache bypassing
inferred← citeshttps://doi.org/10.1145/2925426.2926253openalex-snapshot
Tag-Split Cache for Efficient GPGPU Cache Utilization
inferred← citeshttps://doi.org/10.1145/2925426.2926266openalex-snapshot
Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/3037697.3037709openalex-snapshot
Locality-Aware CTA Clustering for Modern GPUs
inferred← citeshttps://doi.org/10.1145/3079079.3079089openalex-snapshot
Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures
inferred← citeshttps://doi.org/10.1145/3079856.3080239openalex-snapshot
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
inferred← citeshttps://doi.org/10.1145/3093315.3037709openalex-snapshot
Locality-Aware CTA Clustering for Modern GPUs
inferred← citeshttps://doi.org/10.1145/3093336.3037709openalex-snapshot
Locality-Aware CTA Clustering for Modern GPUs
inferred← citeshttps://doi.org/10.1145/3093337.3037709openalex-snapshot
Locality-Aware CTA Clustering for Modern GPUs
inferred← citeshttps://doi.org/10.1145/3140659.3080239openalex-snapshot
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
inferred← citeshttps://doi.org/10.1145/3168831openalex-snapshot
CUDAAdvisor: LLVM-based runtime profiling for modern GPUs
inferred← citeshttps://doi.org/10.1145/3173162.3173195openalex-snapshot
Filtering Translation Bandwidth with Virtual Caching
inferred← citeshttps://doi.org/10.1145/3179541.3168831openalex-snapshot
CUDAAdvisor: LLVM-based runtime profiling for modern GPUs
inferred← citeshttps://doi.org/10.1145/3225058.3225104openalex-snapshot
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection
inferred← citeshttps://doi.org/10.1145/3243176.3243188openalex-snapshot
In-DRAM near-data approximate acceleration for GPUs
inferred← citeshttps://doi.org/10.1145/3269982openalex-snapshot
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1145/3287624.3287633openalex-snapshot
A sharing-aware L1.5D cache for data reuse in GPGPUs
inferred← citeshttps://doi.org/10.1145/3296957.3173195openalex-snapshot
Filtering Translation Bandwidth with Virtual Caching
inferred← citeshttps://doi.org/10.1145/3322127openalex-snapshot
An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns
inferred← citeshttps://doi.org/10.1145/3337821.3337886openalex-snapshot
Compiler-Assisted GPU Thread Throttling for Reduced Cache Contention
inferred← citeshttps://doi.org/10.1145/3358528.3358551openalex-snapshot
Optimization Methods for Computing System in Mobile CPS
inferred← citeshttps://doi.org/10.1145/3406538openalex-snapshot
Inter-kernel Reuse-aware Thread Block Scheduling
inferred← citeshttps://doi.org/10.1145/3422575.3422784openalex-snapshot
DELTA: Validate GPU Memory Profiling with Microbenchmarks
inferred← citeshttps://doi.org/10.1145/3530819openalex-snapshot
A Case for Fine-grain Coherence Specialization in Heterogeneous Systems
inferred← citeshttps://doi.org/10.1145/3581784.3607059openalex-snapshot
Efficient Maximal Biclique Enumeration on GPUs
inferred← citeshttps://doi.org/10.1145/3725798.3725799openalex-snapshot
Optimizing Auto-tuning of OpenMP Offload kernels for performance and power
inferred← citeshttps://doi.org/10.11591/eei.v10i2.2736openalex-snapshot
Architecture exploration of recent GPUs to analyze the efficiency of hardware resources
inferred← citeshttps://doi.org/10.1587/transfun.2020eap1105openalex-snapshot
Instruction Prefetch for Improving GPGPU Performance
inferred← citeshttps://doi.org/10.1631/fitee.1700059openalex-snapshot
CWLP: coordinated warp scheduling and locality-protected cache allocation on GPUs
inferred← citeshttps://doi.org/10.2200/s00848ed1v01y201804cac044openalex-snapshot
General-Purpose Graphics Processor Architectures
inferred← citeshttps://doi.org/10.2298/csis240722021topenalex-snapshot
Demystifying power and performance variations in GPU systems through microarchitectural analysis
inferred← citeshttps://doi.org/10.23919/date.2019.8714911openalex-snapshot
LoSCache: Leveraging Locality Similarity to Build Energy-Efficient GPU L2 Cache
inferred← citeshttps://doi.org/10.32657/10356/72031openalex-snapshot
Usage-pattern-based scheduling schemes for power optimization in multi-core systems
inferred← citeshttps://doi.org/10.3390/jlpea6020005openalex-snapshot
A Survey of Cache Bypassing Techniques
inferred← citeshttps://doi.org/10.48550/arxiv.1802.10280openalex-snapshot
Escoin: Efficient Sparse Convolutional Neural Network Inference on GPUs
inferred← citeshttps://doi.org/10.4995/thesis/10251/125477openalex-snapshot
Efficient L2 Cache Management to Boost GPGPU Performance
inferred← citeshttps://doi.org/10.52549/.v11i4.5014openalex-snapshot
Design and Performance Analysis of a Fast 4-Way Set Associative Cache Controller using Tree Pseudo Least Recently Used Algorithm
inferred← citeshttps://doi.org/10.5821/dissertation-2117-344358openalex-snapshot
High-performance and energy-efficient irregular graph processing on GPU architectures
inferred← citeshttps://doi.org/10.59188/eduvest.v4i12.43139openalex-snapshot
The Role of Cache Memory In Enhancing Microprocessor Performance in PT. Srikandi Sinergi Sakti
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.