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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2011.5749757openalex-snapshot
ACCESS: Smart scheduling for asymmetric cache CMPs
inferredcites →https://doi.org/10.1109/iccd.1993.393415openalex-snapshot
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
inferredcites →https://doi.org/10.1109/iccd.2010.5647608openalex-snapshot
Insertion policy selection using Decision Tree Analysis
inferredcites →https://doi.org/10.1109/iccd.2012.6378661openalex-snapshot
Row buffer locality aware caching policies for hybrid memories
inferredcites →https://doi.org/10.1109/isca.2012.6237027openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferredcites →https://doi.org/10.1109/ispass.2004.1291359openalex-snapshot
Performance evaluation of exclusive cache hierarchies
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/l-ca.2012.2openalex-snapshot
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
inferredcites →https://doi.org/10.1109/micro.2006.7openalex-snapshot
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
inferredcites →https://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferredcites →https://doi.org/10.1109/micro.2010.52openalex-snapshot
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/mm.2012.25openalex-snapshot
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
inferredcites →https://doi.org/10.1109/pact.2009.22openalex-snapshot
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
inferredcites →https://doi.org/10.1145/115952openalex-snapshot
Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/165123.165154openalex-snapshot
Cache write policies and performance
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2000064.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferredcites →https://doi.org/10.1145/2366231.2337195openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/301453.301487openalex-snapshot
On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies
inferredcites →https://doi.org/10.1145/360128.360132openalex-snapshot
Eager writeback - a technique for improving bandwidth utilization
inferredcites →https://doi.org/10.1145/781027.781076openalex-snapshot
Using SimPoint for accurate and efficient simulation
inferredcites →https://doi.org/10.1145/800046.801647openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.5555/1870926.1871148openalex-snapshot
Dueling CLOCK: adaptive cache replacement policy based on the CLOCK algorithm
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11390-016-1617-7openalex-snapshot
A Unified Buffering Management with Set Divisible Cache for PCM Main Memory
inferred← citeshttps://doi.org/10.1016/j.parco.2015.06.002openalex-snapshot
Improving last level shared cache performance through mobile insertion policies (MIP)
inferred← citeshttps://doi.org/10.1109/access.2018.2790381openalex-snapshot
Weighted Greedy Dual Size Frequency Based Caching Replacement Algorithm
inferred← citeshttps://doi.org/10.1109/ccgrid.2017.54openalex-snapshot
Performance Optimization by Dynamically Altering Cache Replacement Algorithm in CPU-GPU Heterogeneous Multi-core Architecture
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00033openalex-snapshot
Designing a Cost-Effective Cache Replacement Policy using Machine Learning
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00022openalex-snapshot
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
inferred← citeshttps://doi.org/10.1109/pdp.2017.81openalex-snapshot
Warstack: Improving LLC Replacement for NVM with a Writeback-Aware Reuse Stack
inferred← citeshttps://doi.org/10.1109/tc.2019.2919287openalex-snapshot
Fast and Energy-Efficient OLAP Data Management on Hybrid Main Memory Systems
inferred← citeshttps://doi.org/10.1145/2989081.2989123openalex-snapshot
Replacement Policies for Heterogeneous Memories
inferred← citeshttps://doi.org/10.1145/3240302.3240310openalex-snapshot
Design guidelines for high-performance SCM hierarchies
inferred← citeshttps://doi.org/10.1145/3695873openalex-snapshot
SuccinctKV: a CPU-efficient LSM-tree Based KV Store with Scan-based Compaction
inferred← citeshttps://doi.org/10.1504/ijcaet.2016.079392openalex-snapshot
A survey of power management techniques for phase change memory
inferred← citeshttps://doi.org/10.23919/date.2018.8342273openalex-snapshot
An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines
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