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Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1023/b:supe.0000014800.27383.8fopenalex-snapshot
Dynamic Partitioning of Shared Cache Memory
inferredcites →https://doi.org/10.1109/date.2010.5457221openalex-snapshot
Energy- and endurance-aware design of phase change memory caches
inferredcites →https://doi.org/10.1109/hpca.1999.744314openalex-snapshot
Dynamically exploiting narrow width operands to improve processor power and performance
inferredcites →https://doi.org/10.1109/hpca.2008.4658653openalex-snapshot
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
inferredcites →https://doi.org/10.1109/hpca.2011.5749752openalex-snapshot
FREE-p: Protecting non-volatile memory against both hard and soft errors
inferredcites →https://doi.org/10.1109/hpca.2013.6522322openalex-snapshot
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations
inferredcites →https://doi.org/10.1109/hpca.2014.6835933openalex-snapshot
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
inferredcites →https://doi.org/10.1109/hpca.2014.6835944openalex-snapshot
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942108openalex-snapshot
Proceedings of the 2019 International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iscas.2014.6865319openalex-snapshot
Register allocation for hybrid register architecture in nonvolatile processors
inferredcites →https://doi.org/10.1109/islped.2011.5993611openalex-snapshot
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
inferredcites →https://doi.org/10.1109/jetcas.2014.2374291openalex-snapshot
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM
inferredcites →https://doi.org/10.1109/l-ca.2006.12openalex-snapshot
Exploiting Narrow Values for Soft Error Tolerance
inferredcites →https://doi.org/10.1109/micro.2006.31openalex-snapshot
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2014.46openalex-snapshot
Futility Scaling: High-Associativity Cache Partitioning
inferredcites →https://doi.org/10.1109/micro.2014.47openalex-snapshot
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
inferredcites →https://doi.org/10.1109/nas.2012.37openalex-snapshot
Wear-Resistant Hybrid Cache Architecture with Phase Change Memory
inferredcites →https://doi.org/10.1109/rtcsa.2014.6910554openalex-snapshot
Enhancing lifetime of NVM-based main memory with bit shifting and flipping
inferredcites →https://doi.org/10.1109/tc.2009.33openalex-snapshot
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1109/tcad.2014.2351581openalex-snapshot
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method
inferredcites →https://doi.org/10.1109/tvlsi.2014.2361150openalex-snapshot
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1735970.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1736020.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1815961.1815980openalex-snapshot
Use ECP, not ECC, for hard failures in resistive memories
inferredcites →https://doi.org/10.1145/2228360.2228581openalex-snapshot
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
inferredcites →https://doi.org/10.1145/2593069.2593153openalex-snapshot
Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination
inferredcites →https://doi.org/10.1145/2627369.2627667openalex-snapshot
Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/360128.360150openalex-snapshot
Dynamic zero compression for cache energy reduction
inferredcites →https://doi.org/10.5555/2016802.2016827openalex-snapshot
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-15663-3_3openalex-snapshot
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques
inferred← citeshttps://doi.org/10.1007/s11227-019-02758-0openalex-snapshot
Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits
inferred← citeshttps://doi.org/10.1007/s11227-022-04394-7openalex-snapshot
Data block manipulation for error rate reduction in STT-MRAM based main memory
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104462openalex-snapshot
An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory
inferred← citeshttps://doi.org/10.1109/tc.2019.2892424openalex-snapshot
Improving the Lifetime of Non-Volatile Cache by Write Restriction
inferred← citeshttps://doi.org/10.1109/tc.2020.2989243openalex-snapshot
NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications
inferred← citeshttps://doi.org/10.1109/tcad.2020.2986320openalex-snapshot
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation
inferred← citeshttps://doi.org/10.1109/tetc.2022.3163438openalex-snapshot
WiSE: W hen Learning Ass i sts Resolving S TT-MRAM E fficiency Challenges
inferred← citeshttps://doi.org/10.1109/vlsid.2019.00091openalex-snapshot
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches
inferred← citeshttps://doi.org/10.1145/3547276.3548513openalex-snapshot
Register-Pressure Aware Predicator for Length Multiplier of RVV
inferred← citeshttps://doi.org/10.1145/3547276.3548515openalex-snapshot
The Support of MLIR HLS Adaptor for LLVM IR
inferred← citeshttps://doi.org/10.1145/3695794.3695803openalex-snapshot
PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC
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