On the public citation graph
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
0 signed · 139 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/ipdps.2010.5470423openalex-snapshot
Optimal loop unrolling for GPGPU programs
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/ispass.2010.5452013openalex-snapshot
Demystifying GPU microarchitecture through microbenchmarking
inferredcites →https://doi.org/10.1109/micro.1999.809463openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.1109/micro.2010.42openalex-snapshot
Understanding the Energy Consumption of Dynamic Random Access Memories
inferredcites →https://doi.org/10.1109/pact.2003.1238022openalex-snapshot
Resolving register bank conflicts for a network processor
inferredcites →https://doi.org/10.1109/sc.1998.10004openalex-snapshot
Automatically Tuned Linear Algebra Software
inferredcites →https://doi.org/10.1145/1693453.1693472openalex-snapshot
Fast tridiagonal solvers on the GPU
inferredcites →https://doi.org/10.1145/1964179.1964185openalex-snapshot
Register packing for cyclic reduction
inferredcites →https://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferredcites →https://doi.org/10.1145/2155620.2155675openalex-snapshot
A compile-time managed multi-level register file hierarchy
inferredcites →https://doi.org/10.1145/339647.339685openalex-snapshot
Reconfigurable caches and their application to media processing
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
inferredcites →https://doi.org/10.21236/ada419598openalex-snapshot
Smart Memories: A Modular Reconfigurable Architecture
inferredcites →https://doi.org/10.5555/320080.320119openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.5555/509058.509096openalex-snapshot
Automatically Tuned Linear Algebra Software
inferredcites →https://doi.org/10.5555/942806.943845openalex-snapshot
Resolving register bank conflicts for a network processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.4104openalex-snapshot
Incorporating selective victim cache into GPGPU for high‐performance computing
inferred← citeshttps://doi.org/10.1002/cpe.5512openalex-snapshot
Static code transformations for thread‐dense memory accesses in GPU computing
inferred← citeshttps://doi.org/10.1007/978-3-319-09873-9_30openalex-snapshot
Power-Aware L1 and L2 Caches for GPGPUs
inferred← citeshttps://doi.org/10.1007/978-3-319-96983-1_17openalex-snapshot
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache
inferred← citeshttps://doi.org/10.1007/s11227-014-1331-6openalex-snapshot
Power-efficient prefetching on GPGPUs
inferred← citeshttps://doi.org/10.1007/s11390-015-1510-9openalex-snapshot
Cooperative Computing Techniques for a Deeply Fused and Heterogeneous Many-Core Processor Architecture
inferred← citeshttps://doi.org/10.1007/s11390-016-1610-1openalex-snapshot
Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs
inferred← citeshttps://doi.org/10.1016/b978-0-12-803738-6.00020-3openalex-snapshot
Architecting the last-level cache for GPUs using STT-MRAM nonvolatile memory
inferred← citeshttps://doi.org/10.1016/j.jpdc.2015.12.003openalex-snapshot
Architecture supported register stash for GPGPU
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.09.001openalex-snapshot
Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.mejo.2023.105825openalex-snapshot
Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.07.012openalex-snapshot
ASHA: An adaptive shared-memory sharing architecture for multi-programmed GPUs
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104301openalex-snapshot
Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures
inferred← citeshttps://doi.org/10.1016/j.parco.2026.103208openalex-snapshot
A comprehensive survey on multi-GPU systems
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0092openalex-snapshot
Cluster‐based approach for improving graphics processing unit performance by inter streaming multiprocessors locality
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7427984openalex-snapshot
Performance-centric register file design for GPUs using racetrack memory
inferred← citeshttps://doi.org/10.1109/cads.2013.6714230openalex-snapshot
ISP: Using idle SMs in hardware-based prefetching
inferred← citeshttps://doi.org/10.1109/cgo.2015.7054184openalex-snapshot
Automatic data placement into GPU on-chip memory resources
inferred← citeshttps://doi.org/10.1109/codes-isss.2013.6659017openalex-snapshot
ARGO: Aging-aware GPGPU register file allocation
inferred← citeshttps://doi.org/10.1109/fccm.2017.59openalex-snapshot
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835970openalex-snapshot
Spare register aware prefetching for graph algorithms on GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056023openalex-snapshot
Coordinated static and dynamic cache bypassing for GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056031openalex-snapshot
Mascar: Speeding up GPU warps by reducing memory pitstops
inferred← citeshttps://doi.org/10.1109/hpca.2018.00041openalex-snapshot
WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00056openalex-snapshot
Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070943openalex-snapshot
Know Your Enemy To Save Cloud Energy: Energy-Performance Characterization of Machine Learning Serving
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys60770.2023.00017openalex-snapshot
ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators
inferred← citeshttps://doi.org/10.1109/iccd63220.2024.00047openalex-snapshot
Advanced Dynamic Scalarisation for RISC-V GPGPUs
inferred← citeshttps://doi.org/10.1109/icisfall51598.2021.9627400openalex-snapshot
A Survey of GPGPU Parallel Processing Architecture Performance Optimization
inferred← citeshttps://doi.org/10.1109/ipdps.2017.81openalex-snapshot
Elastic-Cache: GPU Cache Architecture for Efficient Fine- and Coarse-Grained Cache-Line Management
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00025openalex-snapshot
CIAO: Cache Interference-Aware Throughput-Oriented Architecture and Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.202openalex-snapshot
Reducing Static and Dynamic Power of L1 Data Caches in GPGPUs
inferred← citeshttps://doi.org/10.1109/isca.2016.26openalex-snapshot
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs
inferred← citeshttps://doi.org/10.1109/isca.2016.59openalex-snapshot
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
inferred← citeshttps://doi.org/10.1109/islped.2013.6629259openalex-snapshot
An energy efficient GPGPU memory hierarchy with tiny incoherent caches
inferred← citeshttps://doi.org/10.1109/islped.2015.7273490openalex-snapshot
Bank stealing for conflict mitigation in GPGPU Register File
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00035openalex-snapshot
Enabling Reproducible and Agile Full-System Simulation
inferred← citeshttps://doi.org/10.1109/ispdc.2016.12openalex-snapshot
Applying Victim Cache in High Performance GPGPU Computing
inferred← citeshttps://doi.org/10.1109/les.2024.3351753openalex-snapshot
Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs
inferred← citeshttps://doi.org/10.1109/mcsoc.2016.37openalex-snapshot
A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code Generation
inferred← citeshttps://doi.org/10.1109/micro.2014.11openalex-snapshot
Adaptive Cache Management for Energy-Efficient GPU Computing
inferred← citeshttps://doi.org/10.1109/micro.2014.24openalex-snapshot
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
inferred← citeshttps://doi.org/10.1109/micro.2016.7783717openalex-snapshot
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783718openalex-snapshot
Zorua: A holistic approach to resource virtualization in GPUs
inferred← citeshttps://doi.org/10.1109/micro.2018.00025openalex-snapshot
Rethinking the Memory Hierarchy for Modern Languages
inferred← citeshttps://doi.org/10.1109/micro.2018.00037openalex-snapshot
FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput
inferred← citeshttps://doi.org/10.1109/micro.2018.00067openalex-snapshot
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00029openalex-snapshot
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00098openalex-snapshot
Blenda: Dynamically-Reconfigurable Stacked DRAM
inferred← citeshttps://doi.org/10.1109/mm.2020.3012514openalex-snapshot
Countering Load-to-Use Stalls in the NVIDIA Turing GPU
inferred← citeshttps://doi.org/10.1109/sc.2014.73openalex-snapshot
Scaling the Power Wall: A Path to Exascale
inferred← citeshttps://doi.org/10.1109/sc.2016.76openalex-snapshot
Enabling Efficient Preemption for SIMT Architectures with Lightweight Context Switching
inferred← citeshttps://doi.org/10.1109/synasc.2014.70openalex-snapshot
Register Caching for Stencil Computations on GPUs
inferred← citeshttps://doi.org/10.1109/tc.2015.2417545openalex-snapshot
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs
inferred← citeshttps://doi.org/10.1109/tc.2017.2690855openalex-snapshot
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory
inferred← citeshttps://doi.org/10.1109/tc.2019.2907591openalex-snapshot
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance
inferred← citeshttps://doi.org/10.1109/tcad.2015.2424962openalex-snapshot
An Efficient Compiler Framework for Cache Bypassing on GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2017.2764886openalex-snapshot
Optimizing Cache Bypassing and Warp Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3031895openalex-snapshot
Exploring Applications of STT-RAM in GPU Architectures
inferred← citeshttps://doi.org/10.1109/tmscs.2017.2705139openalex-snapshot
Thoroughly Exploring GPU Buffering Options for Stencil Code by Using an Efficiency Measure and a Performance Model
inferred← citeshttps://doi.org/10.1109/tpds.2016.2546249openalex-snapshot
A Survey of Techniques for Architecting and Managing GPU Register File
inferred← citeshttps://doi.org/10.1109/tpds.2017.2773516openalex-snapshot
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
inferred← citeshttps://doi.org/10.1109/tpds.2022.3154315openalex-snapshot
OSM: Off-Chip Shared Memory for GPUs
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2584623openalex-snapshot
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU
inferred← citeshttps://doi.org/10.1142/s0218126614300025openalex-snapshot
A SURVEY OF TECHNIQUES FOR MANAGING AND LEVERAGING CACHES IN GPUs
inferred← citeshttps://doi.org/10.1142/s0218213015400011openalex-snapshot
A Hybrid Parallel Implementation of the Aho–Corasick and Wu–Manber Algorithms Using NVIDIA CUDA and MPI Evaluated on a Biological Sequence Database
inferred← citeshttps://doi.org/10.1145/2536430.2536434openalex-snapshot
Toward application-specific memory reconfiguration for energy efficiency
inferred← citeshttps://doi.org/10.1145/2597652.2597685openalex-snapshot
Unified on-chip memory allocation for SIMT architecture
inferred← citeshttps://doi.org/10.1145/2636342openalex-snapshot
A Survey of Methods for Analyzing and Improving GPU Energy Efficiency
inferred← citeshttps://doi.org/10.1145/2749469.2750399openalex-snapshot
A case for core-assisted bottleneck acceleration in GPUs
inferred← citeshttps://doi.org/10.1145/2764905openalex-snapshot
Architecting the Last-Level Cache for GPUs using STT-RAM Technology
inferred← citeshttps://doi.org/10.1145/2811402openalex-snapshot
Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency
inferred← citeshttps://doi.org/10.1145/2830772.2830813openalex-snapshot
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs
inferred← citeshttps://doi.org/10.1145/2872887.2750399openalex-snapshot
A case for core-assisted bottleneck acceleration in GPUs
inferred← citeshttps://doi.org/10.1145/2902961.2903022openalex-snapshot
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices
inferred← citeshttps://doi.org/10.1145/2907294.2907298openalex-snapshot
Improving GPU Performance Through Resource Sharing
inferred← citeshttps://doi.org/10.1145/3177964openalex-snapshot
GPU Performance vs. Thread-Level Parallelism
inferred← citeshttps://doi.org/10.1145/3243905openalex-snapshot
Software-Directed Techniques for Improved GPU Register File Utilization
inferred← citeshttps://doi.org/10.1145/3280849openalex-snapshot
Improving Thread-level Parallelism in GPUs Through Expanding Register File to Scratchpad Memory
inferred← citeshttps://doi.org/10.1145/3287624.3287633openalex-snapshot
A sharing-aware L1.5D cache for data reuse in GPGPUs
inferred← citeshttps://doi.org/10.1145/3322127openalex-snapshot
An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns
inferred← citeshttps://doi.org/10.1145/3419973openalex-snapshot
Highly Concurrent Latency-tolerant Register Files for GPUs
inferred← citeshttps://doi.org/10.1145/3466752.3480105openalex-snapshot
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources
inferred← citeshttps://doi.org/10.1145/3649329.3655906openalex-snapshot
SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism
inferred← citeshttps://doi.org/10.1145/3721288openalex-snapshot
PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
inferred← citeshttps://doi.org/10.1145/3760250.3762234openalex-snapshot
CHERI-SIMT: Implementing Capability Memory Protection in GPUs
inferred← citeshttps://doi.org/10.1145/3760782openalex-snapshot
A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs
inferred← citeshttps://doi.org/10.1145/3764862.3768175openalex-snapshot
Towards Memory Specialization: A Case for Long-Term and Short-Term RAM
inferred← citeshttps://doi.org/10.1145/3767110.3767120openalex-snapshot
CMOS+X: Stacking Memories based on Oxide Transistors upon GPGPU Platforms
inferred← citeshttps://doi.org/10.1177/10943420251347461openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
inferred← citeshttps://doi.org/10.12681/eadd/29868openalex-snapshot
Parallel and distributed implementations of multiple and two-dimensional pattern matching algorithms
inferred← citeshttps://doi.org/10.14288/1.0167110openalex-snapshot
GPU computing architecture for irregular parallelism
inferred← citeshttps://doi.org/10.2200/s00611ed1v01y201411cac030openalex-snapshot
Power-Efficient Computer Architectures: Recent Advances
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539342openalex-snapshot
FedCM: Fine-grained Kernel Scheduling and Management to Improve GPU Sharing
inferred← citeshttps://doi.org/10.3850/9783981537079_0394openalex-snapshot
Critical Points Based Register-Concurrency Autotuning for GPUs
inferred← citeshttps://doi.org/10.48550/arxiv.1404.4629openalex-snapshot
A Survey of Methods For Analyzing and Improving GPU Energy Efficiency
inferred← citeshttps://doi.org/10.48550/arxiv.2010.09330openalex-snapshot
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
inferred← citeshttps://doi.org/10.4995/thesis/10251/125477openalex-snapshot
Efficient L2 Cache Management to Boost GPGPU Performance
inferred← citeshttps://doi.org/10.5555/2555692.2555722openalex-snapshot
ARGO: aging-aware GPGPU register file allocation
inferred← citeshttps://doi.org/10.5555/2648668.2648674openalex-snapshot
An energy efficient GPGPU memory hierarchy with tiny incoherent caches
inferred← citeshttps://doi.org/10.5555/2738600.2738604openalex-snapshot
Automatic data placement into GPU on-chip memory resources
inferred← citeshttps://doi.org/10.5555/3014904.3015007openalex-snapshot
Enabling efficient preemption for SIMT architectures with lightweight context switching
inferred← citeshttps://doi.org/10.7282/t3b27zvbopenalex-snapshot
Synergistic Data Placement for GPU On-chip Memory
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.